Showing papers on "VHDL published in 1987"

The IBM VHDL Design System

Abstract: This paper presents the IBM VHDL Design System. This set of Computer Aided Engineering (CAE) design tools, built around the VHSIC Hardware Description Language (VHDL) and developed for IBM internal use, along with other design automation tools, is used by IBM design engineers to develop computer hardware. The function and operation of each piece of the system is described. IBM usage and some of the problems encountered are also discussed.

VISION: VHDL Induced Schematic Imaging on Net-Lists

Abstract: This paper describes a system capable of generating schematic diagrams for gate-level digital logic circuits given only their net-list descriptions in the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL). A combination of algorithmic and heuristic methods are employed to synthesize a schematic drawing which is as aesthetically pleasing and functionally readable to human designers as possible. A methodology for generating schematics which contain feedback loops is presented.

An Interface between VHDL and EDIF

Abstract: The VHSIC Hardware Description Language (VHDL) and the Electronic Design Interchange Format (EDIF) are becoming industry standards for hardware design and documentation. Potential users of these standards are interested in understanding the application range of each standard and the way each standard relates to the other. This paper presents scenarios in which VHDL and EDIF can contribute to different aspects of the design process, as well as the technical issues in providing a design interface between VHDL and EDIF. Both standards are currently being reviewed and revised [1] [2]. In this paper we have used VHDL Version 1076/A [3] and EDIF Version 1 1 0 [4].

Where VHDL Fits within the CAD Environment

Abstract: This paper discusses the relationship of the VHSIC Hardware Description Language (VHDL), the Electronic Design Interchange Format (EDIF), and the Initial Graphics Exchange Specification (IGES) in a Computer Aided Design (CAD) environment.

Design Automation Standards Development

Abstract: ``Creating, modifying, supporting and managing complex electronic systems are dependent upon the ability to communicate the design details from one design discipline to another and to integrate the various types of data representing the many facets of the product description.'' The reliability of complex electronic systems is equally dependent on the ability to communicate the necessary data, throughout a product's life cycle, among those who design and maintain the product. The VHSIC Hardware Description Language (VHDL) and the Electronic Design Interchange Format (EDIF) are two standards that may help to streamline the process. A conceptual schema for shared product data may be used to relate the electrical design environment to the mechanical design and fabrication environment. This paper addresses the design automation standards environment and the relationships being formed between the Design Automation Standards Subcommittee (DASS) and other standardsmaking activities. The ongoing effort within the DASS to develop a range of standards and recommended practices that will aid the electronics industry to achieve necessary data communication capabilities are discussed. Two of the prominent new design automation standards, VHDL and EDIF, are described.

A production-quality UNIX Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) subset analyzer

Abstract: : This paper describes the design and implementation of the Air Force Institute of Technology's (AFIT's) UNIX-based VHDL Analyzer. The purpose of this tool is to facilitate the introduction of VHDL into the academic environment, which may not be able to use the Department of Defense's VMS-based software. This research emphasized two areas: the criteria for a production-quality software product and the design of an efficient Intermediate Representation (IR) that serves as an interface between the Analyzer and other tools in the AFIT VHDL Environment (AVE). Background on other UNIX VHDL analyzers, as well as other IRs, was presented. A two-part IR, based on Dallen's Patois hardware description language and named the VHDL Intermediate Access (VIA), was designed, and examples were given that illustrate its use. Test results showed that the Analyzer passed over 75% of the conformance tests from the VHDL VMS Analyzer Test Suite and performed well in the areas of compile time, memory usage, and disk usage. Recommendations for future research include adding user options to the Analyzer and implementing a design library for VHDL designs.

An algorithm for microcode compaction of VHDL behavioral descriptions

Abstract: We present an algorithm to transform a sequential (vertical microcode) VHDL (VHSIC Hardware Description Language) behavioral description of a digital system design into a parallel (horizontal microcode) VHDL description. Data dependency analysis is performed on the sequential code to identify the parallelism within the code. This parallel VHDL code is targeted for synthesis by the MIMOLA synthesis system.

Interchange of electronic design through VHDL and EIS

Abstract: The need for both robust and unambiguous electronic designs is a direct requirement of the astonishing growth in design and manufacturing capability during recent years. In order to manage the plethora of designs, and have the design data both interchangeable and interoperable, the Very High Speed Integrated Circuits (VHSIC) program is developing two major standards for the electronic design community. The VHSIC Hardware Description Language (VHDL) is designed to be the lingua franca for transmission of design data between designers and their environments. The Engineering Information System (EIS) is designed to ease the integration of data betweeen diverse design automation systems. This paper describes the rationale for the necessity for these two standards and how they provide a synergistic expressive capability across the macrocosm of design environments.