Showing papers on "Wait-for graph published in 1986"

Set theoretic approaches to graph grammars

Abstract: This paper sketches the approaches of a certain branch of graph grammars mainly studied at Erlangen, Osnabruck, Koblenz and Aachen, West Germany. It is named set theoretic, or expression, or algorithmic approach of graph grammars, because its mathematical base is elementary set theory, expressions are used to denote embedding transformations, and the question of applicability and implementation always was regarded of equal importance as theoretical results.

A Feature Space Rule-Based Optical Relational Graph Processor

Abstract: A rule-based optical symbolic and inference processor concept using a relational graph is described. The architecture and its design are discussed and detailed for one example. The system uses a Fourier/polar/Mellin/Fourier transform representation space and the case studies addressed involve aircraft identification and classification. However, the basic rule-based optical-inference relational graph processor concept and architecture are quite general purpose.

Deadlock detection algorithms in distributed database systems

Abstract: In this paper, a centralized deadlock detection algorithm with multiple outstanding requests (CDDMOR) is proposed for use in distributed database systems and transaction-processing systems. This algorithm allows a process to request many resources simultaneously. While a centralized scheme is superior to a completely distributed scheme in terms of performance, a major problem of such a scheme is congestion. Therefore, an important extension to the basic CDDMOR, a partially distributed scheme, is proposed to alleviate the problem of congestion, as well as to take advantage of the result presented by several researchers that global (multisite) deadlocks are infrequent. It takes care of the local (single site) deadlocks without involving other sites and uses centralized deadlock detection only when there is a possibility of global deadlock.

Bit-sliced design of a graph reduction processor

Abstract: Bit-Slice Design of a Graph Reduction Processor Richard P. Vireday Oregon Graduate Center, 1986 Supervising Professor: Richard B. Kieburtz The G-Machine is an abstract architecture t h a t t o supports languages with graph computing models by utilizing software technologies t o provide efficient graph manipulation on sequential machines. Graph computing models are different than those for s tandard imperative languages, and support for graph manipulation is generally lacking on machines designed for s tandard imperative languages. The architecture is stack-based and manipulates graphs via pointers, a pointer stack, and tagged memories. The tags and pointer stack also help provide a n effective method of performing "lazy" evaluation, a computing technique t h a t allows for execution of many complex algorithms. In this thesis, the abstract G-Machine Architecture has been redefined t o provide a ceprocessor implementation. The heart of the G-Machine ceprocessor is the Program Execution Unit (PCU), a conceptually simple processor which can be implemented in a variety of ways. A design for the PCU is shown t h a t is simple t o build and program, utilizes existing technology, and provides complete support for the abstract G-Machine