Precise keeper control of domino logic circuit can significantly increase the speed of operation. However, the positive feedback gain associated with the feedback keeper circuit unduly increases the delay variability. Here, a novel high-speed clock delayed dual keeper (CDDK) domino circuit is presented, which aims at reducing the delay and lower the impact of loop gain on delay variability. In CDDK domino structure, the keeper circuit comprising of two keeper devices is disabled during the initial evaluation phase. This significantly reduces the contention current and thereby the operating speed of the circuit is enhanced. The simulations of the circuits have been carried out for various metrics and the results have been analysed. Furthermore, the Monte-Carlo simulations carried out for 2000 runs on a 128-input OR gate using CDDK structure demonstrate reduced delay variability characteristics due to smaller loop gain of the CDDK domino structure against the conventional domino logic style. The enhanced speed of operation due to reduced contention current is demonstrated. The results are validated through comparison against the conventional domino logic counterpart circuits. The analyses of the circuits are performed using industry standard full-suite Cadence® tools using 90 nm technology library.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2018.5410

Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit

Designers primary goal is to develop the Adder cell with improved performance viz. speed, fixed rise and fall time, as it the fundamental block in VLSI design process. The dynamic logic circuits are far better than the static logic circuits because it consumes less power and speed performance also increased. But, cascading of several blocks in dynamic logic is found to be a wrong analysis. This drawback of increased complexity with mismatched cascading is overcome by using domino logic circuits. By using domino logic circuits, the reduction of noise margins and increase the speed performance of the circuit is achieved. In this paper, domino logic based Manchester carry chain adder (MCC) is designed using FinFET 18nm technology in Cadence virtuoso. It is noticed that 4-bit and an 8-bit Manchester Carry Chain Adder (MCC) using domino logic design consumes less power and reduction in the delay of the proposed circuit compared with the previous architecture. Implementation results reveal that the 4-Bit MCC Adder has delay of 79.45% less compared to the existed standard design and power consumption also reduced to 94.15%.

Comparative Analysis of 8-Bit Manchester Carry Chain Adder Using FinFET at 18nm Technology

Domino circuit topology for high-speed operation, robustness and lower power consumption is quintessential in design of digital systems. In this paper, various high speed and robust mechanisms are ...

Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style

An improved charge-sharing elimination pseudo-domino logic

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic

https://onlinelibrary.wiley.com/doi/pdf/10.4218/etrij.2018-0313

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency by 1.62 times. The logic is designed using Verilog HDL. Synthesis is done on Encounter by Cadence after timing and logic simulation.

Design and implementation of single precision pipelined floating point co-processor

In this paper, a high-performance domino logic style with reduced delay and less delay variability under process parameter variations is presented. An improved control methodology with delayed enabling of the keeper circuit using the clock signal is proposed. This makes the keeper to be idle during the start of the evaluation phase and reduces the contention. It also helps in increasing the speed performance of the circuit. Furthermore, the reduced loop gain due to the modified keeper circuit lessens the delay variations. The proposed keeper control circuits demonstrate delay reduction of 46% compared to the conventional domino logic circuit. The statistical variations of the process parameters using Monte Carlo analysis demonstrate the reduced delay variations to the tune of 48% for 100 runs. The circuits are simulated using Cadence Virtuoso® employing 180 nm technology node libraries.

A. Anita Angeline

Papers

Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style

Design and implementation of single precision pipelined floating point co-processor

High Performance Domino Logic Circuit Design by Contention Reduction