The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special, subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 /spl mu/m CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency. >

VLSI architectures for video compression-a survey

Systolic VLSI architectures for implementing the full-search block-matching algorithm are described. A large range of data rates can be efficiently covered by the proposed architectures. The input bandwidth problem for the search-area data is solved by on-chip line buffers, allowing a low frame-buffer access rate. An architecture for block-scan data input is described in detail. A VLSI realization with a low transistor count can be achieved by linear arrays in conjunction with compact memory blocks based on three-transistor cells. >

Parameterizable VLSI architectures for the full-search block-matching algorithm

The implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented. The chip contains 32 processing elements working in parallel and a random-access memory (RAM) which performs a 16*16 matrix transposition. The structure is highly regular and modular, and thus very efficient for VLSI implementation. The chip was designed for real-time processing of 14.3-MHz sample video data. It performs an equivalent of a half billion multiplications and accumulations per second. Fabricated in 2- mu m double-metal CMOS technology, the chip contains approximately 73000 transistors which occupy a 7.2*7.0-mm/sup 2/ area. The 68-pad die size is 8.3*8.1 mm/sup 2/. It is fully functional and is the first working 16*16 DCT chip. The architecture and accuracy studies for finite-wordlength processing are presented. The circuit design and layout using the symbolic design tool MULGA are described in detail. Possible variations are also discussed for multipurpose (variable transform sizes, forward-inverse transform) applications. >

VLSI implementation of a 16*16 discrete cosine transform

https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=820550

Accuracy vs Efficiency Trade-offs in Optical Flow Algorithms

Two systems are presented for compression of hyperspectral imagery which utilize trellis coded quantization (TCQ). Specifically, the first system uses TCQ to encode transform coefficients resulting from the application of an 8/spl times/8/spl times/8 discrete cosine transform (DCT). The second systems uses DPCM to spectrally decorrelate the data, while a 2D DCT coding scheme is used for spatial decorrelation. Side information and rate allocation strategies are discussed. Entropy-constrained code-books are designed using a modified version of the generalized Lloyd algorithm. These entropy constrained systems achieve compression ratios of greater than 70:1 with average PSNRs of the coded hyperspectral sequences exceeding 40.0 dB. >

Compression of hyperspectral imagery using the 3-D DCT and hybrid DPCM/DCT

A single-chip two-dimensional discrete cosine transform processor is presented. This chip meets the challenge of high throughput rate (13.5 MHz) and versatility (block size from 4*4 to 16*16, and direct and inverse DCT) with a die area as small as 40 mm/sup 2/. An efficient optimized architecture providing high computation power is described. The chip is found to exhibit excellent precision performances. A full-custom approach was chosen because of the required speed and economic reasons (implementation of a low-cost real-time video coder/decoder). The chip uses a 1.25- mu m CMOS technology and contains 114000 transistors on 5.4*7.5 mm/sup 2/. >

A one chip VLSI for real time two-dimensional discrete cosine transform

A VLSI architecture that achieves a single-chip real-time implementation of motion estimation is presented. The case of a block matching algorithm that computes a displacement vector for each block of a segmented image is considered. The versatile architecture of the chip allows displacement vectors to be computed for various sizes of template block and matching window, depending on the pixel rate. The chip computes minimum and maximum values of distances, and the distances can be randomly accessed from the outside. Displacements of +or-7 at video rate or +or-15 for videophone, can be computed for 16*16 blocks. >

A versatile and powerful chip for real-time motion estimation

This communication presents a 2D Discrete Cosine Transform Processor realized with a single chip. Implementing a B.G Lee graph, it can perform DCT computation at the video rate of 13.5 MHz on blocks of a programmable size, from 16*16 to 4*4. Direct or inverse DCT computation is also programmable. The maximum computation error for a direct transform followed by an inverse transform is always better than 1 LSB. A hardwired, mapped architecture has led to a 39 mm2 silicon area for a 1.25μ CMOS 2-metal process.

A 13.5 MHz Single Chip Multiformat Discrete Cosine Transform

A VLSI architecture is introduced to achieve a single-chip real-time implementation of large-kernel convolutions. The architecture provides a way to organize the computation in order to lower the I/O bandwidth to 2 pixels per clock cycle, without increasing the internal storage. As a result, the whole silicon array can be dedicated to computation, without excessive external memory requirements, opening the way to single-chip, very-large-kernel convolutions. As an example, a 16*16 convolution or correlation architecture has been devised based on a 1.2- mu m CMOS process. The same architecture can be used for data processing involving 2-D data convergence. >

A new VLSI architecture for large kernel real time convolution

This paper presents a study of problems encountered when implementing real time image filters. First, the complexity of the algorithms is studied, according to the peculiarities of applications. Then the problem of the system design and its organisation is presented and differents chip architectures are described for various tradeoffs between the architectural parameters. A new architecture used also for motion estimation is mentioned. In the last chapter the problems of the computation operator design is addressed, with elements on different choices for internal oganization of the computation, pipelining and computation format. This study is based on many applications for which VLSI architectures have already been designed and reported. For some of them chip are currently implemented in our laboratories. Linear filtering has been selected for illustration purpose, but this study is also concerned with many other problems of real time image processing, all exhibiting the common feature of a great importance in the architecture of the global managament of data communication and storage.

A. Artieri

Papers

A one chip VLSI for real time two-dimensional discrete cosine transform

A versatile and powerful chip for real-time motion estimation

A 13.5 MHz Single Chip Multiformat Discrete Cosine Transform

A new VLSI architecture for large kernel real time convolution

VLSI Architectures For Image Filtering