This paper reviews the state of the art of field- programmable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic.

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FPGA Design Methodology for Industrial Control Systems—A Review

The history and fundamentals of distributed arithmetic (DA) are presented. Ways to increase the speed of DA multiplication are described. DA is applied to a biquadratic digital filter, providing an example of vector dot-product and vector-matrix-product mechanization. Applications to transformers and nonlinear and/or nonstationary processing with DA are discussed. It is seen that DA is a very efficient means to mechanize computations that are dominated by inner products. >

Applications of distributed arithmetic to digital signal processing: a tutorial review

MPEG-4 is the multimedia standard for combining interactivity, natural and synthetic digital video, audio and computer-graphics Typical applications are: internet, video conferencing, mobile videophones, multimedia cooperative work, teleteaching and games With MPEG-4 the next step from block-based video (ISO/IEC MPEG-1, MPEG-2, CCITT H261, ITU-T H263) to arbitrarily-shaped visual objects is taken This significant step demands a new methodology for system analysis and design to meet the considerably higher flexibility of MPEG-4 Motion estimation is a central part of MPEG-1/2/4 and H261/H263 video compression standards and has attracted much attention in research and industry, for the following reasons: it is computationally the most demanding algorithm of a video encoder (about 60-80% of the total computation time), it has a high impact on the visual quality of a video encoder, and it is not standardized, thus being open to competition Algorithms, Complexity Analysis, and VLSI Architectures for MPEG-4 Motion Estimation covers in detail every single step in the design of a MPEG-1/2/4 or H261/H263 compliant video encoder: Fast motion estimation algorithms Complexity analysis tools Detailed complexity analysis of a software implementation of MPEG-4 video Complexity and visual quality analysis of fast motion estimation algorithms within MPEG-4 Design space on motion estimation VLSI architectures Detailed VLSI design examples of (1) a high throughput and (2) a low-power MPEG-4 motion estimator Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation is an important introduction to numerous algorithmic, architectural and system design aspects of the multimedia standard MPEG-4 As such, all researchers, students and practitioners working in image processing, video coding or system and VLSI design will find this book of interest

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special, subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 /spl mu/m CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency. >

VLSI architectures for video compression-a survey

This paper describes a processor architecture called OneChip, which combines a fixed-logic processor core with reconfigurable logic resources. Using the programmable components of this the performance of speed-critical can be improved by customizing OneChip's execution units, or flexibility can be added to the glue logic interfaces of embedded controller applications. OneChip eliminates the shortcomings of other custom compute machines by tightly integrating its reconfigurable resources into a MIPS-like processor. Speedups of close to 50 over strict software implementations on a MIPS R4400 are achievable for computing the DCT.

OneChip: an FPGA processor with reconfigurable logic

A single-chip two-dimensional discrete cosine transform processor is presented. This chip meets the challenge of high throughput rate (13.5 MHz) and versatility (block size from 4*4 to 16*16, and direct and inverse DCT) with a die area as small as 40 mm/sup 2/. An efficient optimized architecture providing high computation power is described. The chip is found to exhibit excellent precision performances. A full-custom approach was chosen because of the required speed and economic reasons (implementation of a low-cost real-time video coder/decoder). The chip uses a 1.25- mu m CMOS technology and contains 114000 transistors on 5.4*7.5 mm/sup 2/. >

A one chip VLSI for real time two-dimensional discrete cosine transform

Real-time image processing in an application environment needs a set of low-cost implementations of various algorithms. This paper presents a one chip VLSI median filter based on a systolic processor and working at video rate. It includes its own memory and can be used without any image memory for on-line processing. The architectural choices have made it possible to design a small size chip with a high performance level.

VLSI Architecture for a one chip video median filter

This communication presents an optimized architecture providing the computation power and the versatility that are required for the real-time processing of various blocks format (from 4*4 to 16*16) and for direct/inverse Discrete Cosine Transform. To achieve a realistic single chip implementation, different architectures have been compared. Circuits based on the most efficient architecture will be used for a real-time coder/decoder of color images.

An optimized VLSI architecture for a multiformat discrete cosine transform

The Discrete Cosine Transform [1] is a good but computation consuming first step of many image coding and compression algorithms for good quality, low rate transmissions. A low-cost implementation of a high-speed DCT operator would lower the price of CODEC and could open new fields of applications for DCT in real time image processing. This paper presents a one chip operator, achieving a full 16 × 16 DCT computation at video rate. Algorithmic, architectural and implementation choices combined with a careful optimization of the layout have made it possible to design a reasonnable size chip exhibiting such high performance.

N. Demassieux

Papers

VLSI architectures for video compression-a survey

A one chip VLSI for real time two-dimensional discrete cosine transform

VLSI Architecture for a one chip video median filter

An optimized VLSI architecture for a multiformat discrete cosine transform

A single chip video rate 16×16 discrete cosine transform

N. Demassieux

Papers

VLSI architectures for video compression-a survey

A one chip VLSI for real time two-dimensional discrete cosine transform

VLSI Architecture for a one chip video median filter

An optimized VLSI architecture for a multiformat discrete cosine transform

A single chip video rate 16&#215;16 discrete cosine transform

A single chip video rate 16×16 discrete cosine transform