We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.

https://www.pagiamtzis.com/pubs/pagiamtzis-jssc2006.pdf

Content-addressable memory (CAM) circuits and architectures: a tutorial and survey

Even with the significant focus on IP address lookup in the published literature as well as focus on this market by commercial semiconductor vendors, there is still a challenge for router architects to find solutions that simultaneously meet 3 criteria: scaling in terms of lookup speeds as well as table sizes, the ability to perform high speed updates, and the ability to fit into the overall memory architecture of an Level 3 forwarding engine or packet processor with low systems cost overhead. In this paper, we describe a scheme that meets all three criteria. By contrast, published and commercial semiconductor solutions meet some but not all of these three criteria.For example, many approaches that provide dense tables have poor update times; others require large amounts of expensive high speed memory dedicated to this application. Many IP address lookup approaches do not take into account the flexibility of ASICs or the structure of modern high speed memory technologies such as RLDRAM[1] and FCRAM[2]. In this paper, we present a family of IP lookup schemes using a data structure that compactly encodes large prefix tables in order to address the criteria listed above. We also present a series of optimizations to the core algorithm that allows the memory access width of the algorithm to be reduced at the cost of memory references or allocated memory. Such flexibility in performance versus density is an important feature for the lookup engine of routers that may be deployed in different networks with varying requirements on address lookup length and table density (e.g. global IPv4 networks, global v6, VPN based v4 networks, MPLS, and IP tunneling encapsulation points).

Tree bitmap: hardware/software IP lookups with incremental updates

CAMs are the most popular practical method for implementing packet classification in high performance routers. Their principal drawbacks are high power consumption and inefficient representation of filters with port ranges. A recent paper [Narlikar, et al., 2003] showed how partitioned TCAMs could be used to implement IP route lookup with dramatically lower power consumption. We extend the ideas in [Narlikar, et al., 2003] to address the more challenging problem of general packet classification. We describe two extensions to the standard TCAM architecture. The first organizes the TCAM as a two level hierarchy in which an index block is used to enable/disable the querying of the main storage blocks. The second incorporates circuits for range comparisons directly within the TCAM memory array. Extended TCAMs can deliver high performance (100 million lookups per second) for large filter sets (100,000 filters), while reducing power consumption by a factor of ten and improving space efficiency by a factor of three.

https://www.arl.wustl.edu/Publications/2000-04/icnp03pc.pdf

Packet classification using extended TCAMs

This paper presents two techniques to reduce power consumption in content-addressable memories (CAMs). The first technique is to pipeline the search operation by breaking the match-lines into several segments. Since most stored words fail to match in their first segments, the search operation is discontinued for subsequent segments, hence reducing power. The second technique is to broadcast small-swing search data on less capacitive global search-lines, and only amplify this signal to full swing on a shorter local search-line. As few match-line segments are active, few local search-lines will be enabled, again saving power. We have employed the proposed schemes in a 1024/spl times/144-bit ternary CAM in 1.8-V 0.18-/spl mu/m CMOS, illustrating an overall power reduction of 60% compared to a nonpipelined, nonhierarchical architecture. The ternary CAM achieves a 7-ns search cycle time at 2.89fJ/bit/search.

A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme

We examine the feasibility of introducing power management schemes in network devices in the LAN. Specifically, we investigate the possibility of putting various components on LAN switches to sleep during periods of low traffic activity. Traffic collected in our LAN indicates that there are significant periods of inactivity on specific switch interfaces. Using an abstract sleep model devised for LAN switches, we examine the potential energy savings possible for different times of day and different interfaces (e.g., interfaces connecting to hosts to switches, or interfaces connecting switches, or interfaces connecting switches and routers). Algorithms developed for sleeping, based on periodic protocol behavior as well as traffic estimation are shown to be capable of conserving significant amounts of energy. Our results show that sleeping is indeed feasible in the LAN and in some cases, with very little impact on other protocols. However, we note that in order to maximize energy savings while minimizing sleep-related losses, we need hardware that supports sleeping.

https://ieee-icnp.org/2004/papers/9-4.pdf

A feasibility study for power management in LAN switches

Ternary content-addressable memories (TCAMs) are becoming very popular for designing high-throughput forwarding engines on routers: they are fast, cost-effective and simple to manage. However, a major drawback of TCAMs is their high power consumption. This paper presents architectures and algorithms for making TCAM-based routing tables more power efficient. The proposed architectures and algorithms are simple to implement, use commodity TCAMs, and provide worst-case power consumption guarantees (independent of routing table contents).

/pdf/coolcams-power-efficient-tcams-for-forwarding-engines-nw32dntn2p.pdf

Coolcams: power-efficient TCAMs for forwarding engines

The challenge is to develop an easily usable protocol development framework that combines the flexibility of layered implementations, the efficiency of tightly-coupled monolithic implementations and the correctness achievable using high-level protocol validation languages. This challenge is addressed by a language-based framework that introduces a new protocol specification language called Promela++. The framework consists of a protocol verification tool and an optimizing compiler that generates efficient protocol code from Promela++ specifications. Promela++ is based on the Promela protocol validation language and has been designed with a rich set of domain-specific constructs. These constructs facilitate the task of protocol specification as well as enable the Promela++ compiler to perform domain-specific optimizations. The Promela++ compiler can also automatically transform protocol specifications in Promela++ to protocol models in Promela. The article presents a new language that unites the twin goals of checking protocol correctness using model checkers, and efficient protocol construction using optimizing compilers, under a single framework; exploits language design to provide mechanisms that simultaneously ease programming and enable generation of efficient protocol code; and demonstrates the effectiveness of this approach by doing a complete evaluation of multiple protocol implementations in Promela++.

A. Basu

Papers

Coolcams: power-efficient TCAMs for forwarding engines

Promela++: a language for constructing correct and efficient protocols