Nanotechnologies are being applied to microelectronics packaging, primarily in the applications of nanoparticle nanocomposites, or in the exploitation of the superior mechanical, electrical, or thermal properties of carbon nanotubes. Composite materials are studied for high-k dielectrics, electrically conductive adhesives, conductive "inks," underfill fillers, and solder enhancement. These trends are demonstrated by paper presentations over the past few years at ECTC and other conferences, which show research to be concentrated in relatively few laboratories, with little work being done on the packaging requirements of the new nanoelectronics technologies. Future needs (predictably) include education and software development

/pdf/nanopackaging-nanotechnologies-and-electronics-packaging-q0ut63qr4f.pdf

Nanopackaging: Nanotechnologies and Electronics Packaging

A novel die-attach joining technique based on low-temperature film sintering of nanoporous Cu is demonstrated Nanoporous Cu films are proposed as a low-cost replacement of nano-sintering pastes with the following benefits: (i) synthesis by electrochemical dealloying, compatible with standard lithography processes; (ii) no organic content to minimize risks of voiding and corrosion; and (iii) controllable physical properties post sintering through tailorable initial nanostructure and morphology As a first proof-of-concept, thin films of nanoporous Cu with 25–50nm feature size and ∼60% relative density were synthesized by dealloying of Cu-Si films The nanoporous Cu films were then sintered on bulk Cu metallizations at temperatures of 200–250°C for 5–15min with an applied pressure of 6–9MPa, in reducing atmosphere A maximum shear strength of 42kgf was achieved and analysis of the fracture profiles showed failure through the sintered joints, confirming strong metallurgical bonding to bulk Cu Cross-sections of joints formed at 200°C and 250°C −15min observed by SEM showed relative density as high as 85%, achieved for the first time with sintered copper

Low-temperature, organics-free sintering of nanoporous copper for reliable, high-temperature and high-power die-attach interconnections

Solderless bonding with nanoporous copper as interlayer for high-temperature applications

Many power semiconductor devices now require high tolerance of current density and reliability at high temperature, therefore Cu-Cu bonding using an insert material has raised the level of concerns for its great thermal stability and conductivity. In this study, a low-pressure bonding process was developed to achieve a Cu-Cu bonding using preoxidized Cu microparticles under formic acid atmosphere. The Cu microparticles were preoxidized to generate oxide films and Cu oxide nanostructures, which were then reduced and bonded at 300 °C under formic acid atmosphere to achieve a Cu-Cu bonding. Shear strength of the Cu-Cu bondings were tested to optimize the parameters of bonding process. Fracture surfaces of the Cu-Cu bonding, as well as cross-sectional microstructures, were observed by scanning electrical microscope (SEM) and components were identified by X-ray diffraction (XRD) to investigate the bonding mechanism. The findings reveal that the oxide films and the nanostructures play key roles in this reduction bonding process, which is a promising method to obtain a Cu-Cu bonding satisfying the requirements of power device packaging.

A Cu-Cu Bonding Method Using Preoxidized Cu Microparticles under Formic Acid Atmosphere

We investigate the influential factor in low-temperature bonding of silicon dioxide. Two surfaces were formed by thermal oxidation and plasma-enhanced chemical vapor deposition with 50 nm thick. Surface characterization by atomic force microscopy. Wafer cleaning by piranha, surface-activated by oxygen plasma, pre-bonding at room temperature and post-bonding anneal by 100–400 degrees Celsius in 0.03 Pascal for 1 hour. Bonding area was tested by dicing machine that PECVD silicon dioxide showed weak bonding, whereas oxide from thermal oxidation showed good results between 200–400 degrees Celsius. Thus surface roughness and annealing temperature are an influential factor of low-temperature bonding of silicon dioxide.

Influential factors in low-temperature direct bonding of silicon dioxide

We explore a methodology for patterned copper nanoparticle paste for 3D interconnect applications in wafer to wafer (W2W) bonding. A novel fine pitch thermal compression bonding process (sintering) with coated copper nanoparticle paste was developed. Most of the particle size is between 10–30 nm. Lithographically defined stencil printing using photoresist and lift-off was used to apply and pattern the paste. Variations in sintering process parameters, such as: pressure, geometry and ambient atmosphere, were studied. Compared to Sn-Ag-Cu (SAC) microsolder bumps, we achieved better interconnect resistivity after sintering at 260 °C for 10 min, in a 700 mBar hydrogen forming gas (H 2 /N 2 ) environment. The electrical resistivity was 7.84 ± 1.45 µΩ·cm, which is about 4.6 times that of bulk copper. In addition, metallic nanoparticle interconnect porosity can influence the electrical properties of the interconnect. Consequently, we investigated the porosity effect on conductivity using finite element simulation. A linear relationship between the equivalent conductivity and particle overlapping ratio was found.

/pdf/3d-interconnect-technology-based-on-low-temperature-copper-1x5hmjn6n3.pdf

3D interconnect technology based on low temperature copper nanoparticle sintering

We explored the properties and performance of copper-based metallic nanoparticle paste (MNPs) for interconnects applications in 3D heterogeneous integration. A patterning method was developed to process micron sized sintered MNPs structures. This enables the fabrication of IC interconnect test structures to characterise specific resistivity sintered MNPs and the contact resistances of sintered MNP to bulk copper (bCu) which was respectively 78.4 mOhm.micrometer and 0.23 Ohm.micrometer2. In situ XRD analysis showed no oxidation of MNPs at processing temperatures below 100 oC. When Copper based MNPs are sintered under forming gas conditions, no oxidation of copper is measured. With in situ TEM at a temperature range of 220 -- 260 oC local melting of copper nanoparticles was observed. This is in agreement with the electrical measurements, the resistivity and contact resistance are considerably reduced when MNPs is sintered in this temperature range. Copper-based MNPs is successfully applied as die attach and wafer to wafer (W2W) bonding. However, for W2W bonding, the specific contact resistance was 800 Ohm.micrometer2.

Metallic Nanoparticle Based Interconnect for Heterogeneous 3D Integration

High-performance IC-to-antenna interconnection is one of the key enablers for the mass production of high-end millimeter wave (mmW) radar systems above 100 GHz. In this work, a radar system with an on-package antenna array working at 122 GHz is presented. The antenna is placed on top of the molded package and the antenna-to-chip interconnection is realized by through-polymer via (TPV) technology. The detailed fabrication process of the radar antenna-in-package (AiP) with TPV is discussed. The results from the functional tests of the radar AiP are presented and benchmarked to a commercial quad-flat no-leads (QFN) package with an open antenna cavity. The detection margin between the echo signal and the constant false alarm rate (CFAR) threshold is approximately 10 dB higher for the TPV radar AiP compared with the benchmarked commercial QFN package.

Antenna-in-Package (AiP) Using Through-Polymer Vias (TPVs) for a 122-GHz Radar Chip

Techniques for the bonding of wafers and dies at low temperature are investigated. Controlled wet etching using acids is used to bond SiO2-SiO2 and Al-Al chips at room temperature. The bond strength is evaluated using die-shear tests. Infrared imaging and SEM analysis are used to inspect the bonding interface. The results are compared with data from fusion bonding experiments. Relatively high bond bond strengths for SiO2 and Al-terminated chips are achieved using bonding at room temperature.

Low temperature hybrid wafer bonding for 3D integration


 Sintered silver materials (with and without epoxy matrices) are used in microelectronics, as high-temperature interconnect materials, and also as conductor trace materials in printed electronic circuitry. The sintering process results in an interconnected assemblage of discrete agglomerated particles. This results in intrinsic length-scale effects under the action of different stress gradients. In other words, the effective homogenized average continuum-scale material behavior changes with the local magnitude of the stress gradients. Consequently, regions of sharp, localized stress concentrations have to be modeled with different effective continuum material properties, compared with the properties that are relevant for regions that have a uniform stress field. In this study, the focus in on the effective creep behavior, in particular. This length-scale effect is empirically explored in this study using nanoindentation with indenters of different tip radii, causing different stress gradients. Properties estimated by each indenter are compared to demonstrate the dependence of the effective continuum properties on the local length scale effects (generated by the ratio of the tip radius to the characteristic discrete dimension of the sintered particles).

A. Damian

Papers

3D interconnect technology based on low temperature copper nanoparticle sintering

Metallic Nanoparticle Based Interconnect for Heterogeneous 3D Integration

Antenna-in-Package (AiP) Using Through-Polymer Vias (TPVs) for a 122-GHz Radar Chip

Low temperature hybrid wafer bonding for 3D integration

Length-Scale Effects in Average Viscoplastic Behavior of Sintered Silver Materials: Empirical Exploration With Indentation Methods