This paper presents novel one bit arithmetic and logical unit (ALU) design using basic reversible gates. Two designs for both the arithmetic and the logical unit are proposed and one design for the control unit is also put forward. These designs are integrated together to give four complete ALU designs. Each of the proposed design has been implemented in Verilog HDL using Xilinx ISE Suite 14.1 software to verify its functionality. The proposed designs are compared based on quantum cost, garbage outputs and ancilla inputs with their existing counterparts. The simplicity and the reduced quantum cost of the proposed ALU designs, when compared to the existing ones, makes them ideal candidates to be used as modules in quantum computers. The proposed ALUs extend their applications to cryptography, machine learning and nanotechnology.

An Arithmetic and Logical Unit using Reversible Gates

The semiconductor circuits dissipate energy in the form of binary digits. This dissipation of energy is in the form of power consumption. ALU is complex circuit and is one of many components within CPU. It performs mathematical and bitwise operations. This paper proposes a new low power 8 bit ALU digital circuit for nano scale regions. The proposed ALU has two 4x1 data selectors, 2x4 decoder and an adder circuit as sub modules. The output of 2x4 decoder is connected to 3 input NAND, AND, OR, XOR gates.  With the help of selection lines of multiplexer the conventional operations of ALU such as logical operations are performed. This proposed ALU caters the need of digital signal processing tools. Present ALU structure is simulated in Linux Computer using Cadence Virtuoso software and implemented in 180mm technology. The proposed ALU has delay of 386.0ps and average power of 677.2uW. The power delay product shows 65.58 % improvement when compared to the conventional 8-bit ALU design

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Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector

In the recent times most of the advanced circuits designing projects are using reversible logic since it is helping to decrease the configuration dependent warmth scattering. This allows vitality free calculation, high range of circuit density and better testing provisions. A novel structure for Reversible 16-bit ALU is demonstrated in this paper using fast Vedic multiplier which is planned by falling 1-bit ALUs. Control unit and snake unit are having a significant role to be played in the 1-bit ALU. Peres door was used in the control unit and Haghparast and Navi Gate (HNG) were used for viper unit. The hugest part of this paper is that when contrasted with different papers, this ALU configuration has diminished door check, and transistor tally. A usage depends on Field Programmable Gate Arrays (FPGA) spartan3E XC3S500E which gives client adaptability to a programmable arrangements and bringing down the expense. Power also reduced by 6% when compared with the best existing.

VLSI Design and Synthesis of Reduced Power and High Speed ALU Using Reversible Gates and Vedic Multiplier

Arithmetic and Logical Unit (ALU) is one of the key aspects of the digital world. In generally, it requires a colossal amount of power. This paper outlines a new design of one-bit Parity Preserving Reversible ALU circuit. To design the ALU with low power dissipation, we have used the concept of Reversible Logic computation. Conventional Circuits dissipate an enormous amount of power due to the loss of information bits in computation, but Reversible Circuits has no data loss as one on one mapping between outputs and inputs which leads to the minimization of power dissipation. In our design, we have used Parity Preserving Reversible Gates which are having Fault tolerance property as fault occurring at internal nodes results in an error at the output. So, Parity Preserving Reversible Gates is the one in which Output Parity remains same as of the Inputs. The aimed ALU has been carried out using Xilinx ISE 14.7 version software in Verilog HDL. To demonstrate the efficiency of proposed Parity Preserving Reversible Arithmetic and Logical Unit, each subpart is shown in terms of various parameters such as Quantum cost, Ancilla Inputs, Gate Count and Garbage Outputs and also a comparison with existing work is shown. The intended design is far better than the existing one because of its fault-tolerant capabilities. The proposed ALU extends its application over DNA mapping, Optical computation, cryptography, nanotechnology, quantum computing and digital signal processing.

Design of Parity Preserving Arithmetic and Logic Unit using Reversible Logic Gates

If there is no loss of information with respect to the states of a process it is termed as reversibility in computing. It is possible to recover any previous states by reverse computing, which is called as logical changeability. Logical changeability is achieved only by using physical changeability. Physical changeability is a method that does not emits energy when applied to heat. Reversibility is a productive technique to reduce power dissipation in low and medium power circuits. This paper presents 8-bit and 16-bit reversible ALU designs. Comparison of the performance parameters- area, power and LUT of the ALU designs is shown.

Design of 8 bit and 16 bit Reversible ALU for Low Power Applications

Conventional Complementary metal oxide semiconductor circuits (CMOS) dissipate energy in the form of bits of information. This dissipation of energy is in the form of power dissipation and plays a very important role as far as low power design is considered. Today, most digital circuits are being designed using Reversible Logic. Design based on Reversible Logic helps in reducing heat dissipation, allowing nearly energy free computation, allowing higher circuit densities and enabling better testing of faults. In this paper, a novel design for a Reversible 8-bit ALU is proposed. The 8-bit ALU is designed by cascading 1-bit ALUs. The two major units of a 1-bit ALU are the control unit and the adder unit. For the control unit, the Control Output Gate (COG) has been used and for the adder unit the Haghparast and Navi Gate (HNG) has been used. The most significant aspect of this paper is that as compared to other papers, this ALU design has reduced gate count, and transistor count. The propagation delay was found to be significantly lesser at a value of 5.52ns when compared with the value of 8.29ns for an existing design. Simulation and verification of the proposed design was performed using Cadence 180nm technology software tool.

A Deeptha

Papers

Design and optimization of 8 bit ALU using reversible logic