Multi-objective cluster head selection using fitness averaged rider optimization algorithm for IoT networks in smart cities

Arrhythmia Classification with ECG signals based on the Optimization-Enabled Deep Convolutional Neural Network.

Agriculture is the main source of wealth, and its contribution is essential to humans. However, several obstacles faced by the farmers are due to different kinds of plant diseases. The determination and anticipation of plant diseases are the major concerns and should be considered for maximizing productivity. This paper proposes an effective image processing method for plant disease identification. In this research, the input image is subjected to the pre-processing phase for removing the noise and artifacts present in the image. After obtaining the pre-processed image, it is subjected to the segmentation phase for obtaining the segments using piecewise fuzzy C-means clustering (piFCM). Each segment undergoes a feature extraction phase in which the texture features are extracted, which involves information gain, histogram of oriented gradients (HOG), and entropy. The obtained texture features are subjected to the classification phase, which uses the deep belief network (DBN). Here, the proposed Rider-CSA is employed for training the DBN. The proposed Rider-CSA is designed by integrating the rider optimization algorithm (ROA) and Cuckoo Search (CS). The experimental results proved that the proposed Rider-CSA-DBN outperformed other existing methods with maximal accuracy of 0.877, sensitivity of 0.862, and the specificity of 0.877, respectively.

Deep neural network based Rider-Cuckoo Search Algorithm for plant disease detection

Analog circuits are one of the most commonly used components in industrial equipment. Circuit failure may lead to significant causalities and even enormous financial losses. To cope with this problem, a novel deep learning strategy based on the cross-wavelet transform (XWT) and generative adversarial networks (GANs) is proposed for analog-circuit fault diagnosis. Different from the traditional methods that simply apply the amplitude characteristic on the time–frequency plane, XWT is applied to obtain the spectral images of the fault signals that can be used to capture the comprehensive features with the involvement of the amplitude, phase, and coherence characteristics. Furthermore, a data-regularization trick is employed on these spectral images to construct three-channel feature images data. The input data can reflect the complex relationship effectively between the measured signals and the feature space, with abundant information of multiple domains on the time–frequency plane. Finally, the different distributions for various fault conditions can be learned by the proposed GAN. The adversarial training manner of the generative network and the discriminative network of the GAN can not only mine the complex nonlinear relationship between the root cause of the failure and the signal signature but also alleviate the problem of overfitting that is caused by the limited availability of the training samples. Furthermore, we expand the GAN to a supervised classifier with the coordinative usage of two auxiliary classifiers, and two convolution neural networks are adopted to establish the basic structure of the proposed model. The comparisons of classification performance with other methods indicate that the proposed approach has good potential for analog-circuit fault diagnosis.

Generative Adversarial Networks With Comprehensive Wavelet Feature for Fault Diagnosis of Analog Circuits

The present study applies the one-dimensional convolutional neural network (1D-CNN) to propose an intelligent approach of the feature extraction for the analog circuit diagnosis. The raw signals based on various soft faults from the output terminal of the circuit under test (CUT) are collected with appropriate data acquisition system to implement a data-driven fault diagnosis. The data-driven diagnosis process is typically encapsulated in two distinct blocks, including the feature extraction and the classification. In this study, the designed 1D-CNN model efficiently combines the aforementioned two phases into a single diagnosis body with fast learning rate and accurate classification. The main advantages of the 1D-CNN are: 1) it can be directly established to the raw signal with proper training so that it is more applicable in real applications; 2) its compact architecture and configuration has reasonable applicability in complex analog circuits; 3) convolutional kernels guarantee that the hierarchical features can be extracted from raw data with better anti-interference performance. Moreover, since the method can extract high-level features of raw signals, it resolves the necessity to employ other per-processing methods for the hand-crafted feature transformation. The performance of the proposed 1D-CNN model is evaluated through three benchmark circuits on the SIMULINK platform. Obtained results are compared with other intelligent fault diagnosis methods. The experimental results show that the 1D-CNN can be utilized effectively as the feature exactor and faults classifier for analog circuits.

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Data-Driven Feature Extraction for Analog Circuit Fault Diagnosis Using 1-D Convolutional Neural Network

Fault diagnosis in electronic circuits is an emerging area of research, where fully automated diagnosis systems are being developed for the investigation of the circuits. Developing test methods for the diagnosis of faults in analog circuits is still a complex task. Consequently, a technique for the fault diagnosis in analog circuits is designed by proposing a new optimization algorithm, named, rider optimization algorithm (ROA). The development of ROA is based on a group of riders, racing toward a target location. Moreover, a classifier, termed RideNN, is developed by including the proposed algorithm as the training algorithm for the neural network (NN). RideNN, along with the orthogonal transformation and Bhattacharyya coefficient, is applied for the fault diagnosis of analog circuits. The proposed technique is experimented using three basic circuits, such as triangular wave generator (TWG), low noise bipolar transistor amplifier (BTA), and differentiator (DIF) and an application circuit, solar power converter (SPC). The performance is evaluated using two evaluation metrics, namely, accuracy (ACC) and false alarm ratio (FAR). The analysis results show that the proposed technique attains an ACC of 99.9% in TWG, 99.9% in BTA, 99% in DIF, and 95% in SPC without noise.

RideNN: A New Rider Optimization Algorithm-Based Neural Network for Fault Diagnosis in Analog Circuits

Due to the wide range of applications of electronic circuits in the recent years, the fault diagnosis in electronic circuits is a foremost problem. The main purpose of the fault diagnosis technique is isolating the faults present in the electronic circuits and also, detecting the fault which affects the safety and performance of the system. For various real-time applications of fault diagnosis, literature presents several techniques for detecting the faults in electronic circuits. In this paper, reviews on the research based on the fault diagnosis techniques which are all gained much attention are comprehended. Accordingly, 114 research papers related to the fault diagnosis are reviewed and analyzed based on the various objectives. In this review, we present the taxonomy of the fault detection in analog circuits and discuss the state of the art algorithms with various advantages and major drawbacks. The comprehensive analysis is carried out on finding the coverage of the publishers, faults, circuits, methods, simulation tools, and metrics. This critical review finally discusses the research challenges that are still available in the existing techniques and the way to extend the current research is also examined.

A survey on fault diagnosis of analog circuits: Taxonomy and state of the art

Fault prediction in the analog circuits is a serious problem to be addressed on an immediate basis, as traditionally, the faults in the analog circuits are diagnosed only after their occurrence. Since the outcome of the faults creates highly expensive scenarios in case of the analog circuit industry, there is a need for an effective prediction model that keeps track of the faults prior to their occurrence. Accordingly, this article focuses on the fault prediction model in analog circuits using proposed deep model called, Rider-deep-long short-term memory (LSTM). Here, the significance and precision of the prediction relies on the fault indicator, which is computed based on three distance measures, such as mahalanobis distance, Euclidean distance, and angular distance, and thereby, enables an effective health estimation of the circuit. The estimation is effectively solved using the Rider-deep-LSTM, which is the integration of proposed Rider-Adam algorithm in deep-LSTM, for training the model parameters. The proposed prediction method acquires the Pearson correlation coefficient of 0.9973 and 0.9919 while using the circuits, such as solar power converter and low noise bipolar transistor amplifier.

Rider-Deep-LSTM Network for Hybrid Distance Score-Based Fault Prediction in Analog Circuits

Memories are integral parts of most of the digital devices and hence reducing power consumption of memory is very important in improving the system performance, efficiency and stability. Most of the embedded and portable devices use SRAM cells because of their ease of use as well as low standby leakage. Standard CMOS 6T SRAM cell uses two bit-lines and a word line for both read and write operations. This 6T SRAM cell consumes more power and shows poor stability at small feature sizes with low power supply. During read operation, the stability drastically decreases due to the voltage division between the access and driver transistors. In this paper new 7T SRAM cell is proposed, which uses single bit-line for both read and write operations. Power consumption is reduced because of single bit line usage and read stability is very high compared to conventional 6T SRAM cell. Proposed cell also provides high static noise margins (SNMs). The proposed 7T SRAM cell is compared with conventional 6T SRAM cell in terms of power consumed, delay and SNMs. The Proposed 7T SRAM cell consumes 22.03% less power for write `0' operation, 17.33% less power for write `1' operation, 17.52% less power for read `0' operation and 21.36% less power for read `1' operation compared to conventional 6T SRAM cell. The proposed cell has 2.64 times SNM in read state; 1.082 times SNM in hold state and 1.064 times SNM in write 0 state compared to conventional 6T SRAM cell. Schematics are drawn using virtuoso ADE of Cadence, and all simulations are carried out using Cadence Spectre Analyzer with 90nm Technology library at 1.8V VDD.

Single bit-line 7T SRAM cell for low power and high SNM

Conventional Complementary metal oxide semiconductor circuits (CMOS) dissipate energy in the form of bits of information. This dissipation of energy is in the form of power dissipation and plays a very important role as far as low power design is considered. Today, most digital circuits are being designed using Reversible Logic. Design based on Reversible Logic helps in reducing heat dissipation, allowing nearly energy free computation, allowing higher circuit densities and enabling better testing of faults. In this paper, a novel design for a Reversible 8-bit ALU is proposed. The 8-bit ALU is designed by cascading 1-bit ALUs. The two major units of a 1-bit ALU are the control unit and the adder unit. For the control unit, the Control Output Gate (COG) has been used and for the adder unit the Haghparast and Navi Gate (HNG) has been used. The most significant aspect of this paper is that as compared to other papers, this ALU design has reduced gate count, and transistor count. The propagation delay was found to be significantly lesser at a value of 5.52ns when compared with the value of 8.29ns for an existing design. Simulation and verification of the proposed design was performed using Cadence 180nm technology software tool.

B. S. Kariyappa

Papers

RideNN: A New Rider Optimization Algorithm-Based Neural Network for Fault Diagnosis in Analog Circuits

A survey on fault diagnosis of analog circuits: Taxonomy and state of the art

Rider-Deep-LSTM Network for Hybrid Distance Score-Based Fault Prediction in Analog Circuits

Single bit-line 7T SRAM cell for low power and high SNM

Design and optimization of 8 bit ALU using reversible logic