This book provides the most basic problems, concepts, and well-established results from the topological structure and analysis of interconnection networks in the graph-theoretic language. It covers the basic principles and methods of network design, several well-known networks such as hypercubes, de Bruijn digraphs, Kautz digraphs, double loop, and other networks, and the newest parameters to measure performance of fault-tolerant networks such as Menger number, Rabin number, fault-tolerant diameter, wide-diameter, restricted connectivity, and (l,w)-dominating number. Audience: The book is suitable for those readers who are working on or intend to start research in design analysis of the topological structure of interconnection networks, particularly undergraduates and postgraduates specializing in computer science and applied mathematics.

Topological Structure and Analysis of Interconnection Networks

This survey provides a comprehensive and unified analysis of symmetry in a wide variety of Cayley graphs of permutation groups. These include the star graph, bubble-sort graph, modified bubble-sort graph, complete-transposition graph, prefix-reversal graph, alternating-group graph, binary and base-b (b ≥ 3) hypercube, cube connected cycles, bisectional graph, folded hypercube and binary orthogonal graph. In addition, we also define a variety of generalizations of the hypercube and orthogonal graphs. The types of symmetry analyzed include vertex and edge transitivity, distance regularity and distance transitivity. Since these notions of symmetry depend on the shortest paths, as a by product we also describe the shortest path routing algorithms for these graphs. We present a number of open problems related to the networks described in this paper.

Symmetry in interconnection networks based on Cayley graphs of permutation groups: a survey

Optoelectronic interconnections can provide a practical solution for the ever increasing communication bottleneck problems when combining a multitude of information processing units to perform a function. As research activities progress in the field of serial or parallel board-to-board and module-to-module interconnections, some of the research focus has shifted to smaller physical dimensions, like intra-module interconnections, which combines optoelectronic interconnections, multichip module packaging, and microelectromechanical system (MEMS) technologies at the module level. The present invention provides integrated optical input/output (I/O) couplers on multichip modules (MCMs) using micro-machined silicon mirrors that are used with optoelectronic multichip modules (OE-MCMs). The present invention used microstructures that integrate optical waveguide networks, multilayer electrical transmission line networks, micro-machined silicon mirrors, and C4-bonded photonic devices into a single structure. Using both sides of the silicon wafers, multiple metal layers and optical waveguide layers are fabricated for all types of metal or optical waveguide materials. The input/output coupling arrangement utilizes a combination of micro-machined silicon mirrors and through-holes across OE-MCM, integrated together into a single package. Fabrication strategies and possible applications of the invention are disclosed herein.

Method and apparatus for providing a seamless electrical/optical multi-layer micro-opto-electro-mechanical system assembly

Interconnection networks play a crucial role in the performance of parallel systems. This paper introduces a new interconnection topology that is called the hierarchical hypercube (HHC). This topology is suitable for massively parallel systems with thousands of processors. An appealing property of this network is the low number of connections per processor, which enhances the VLSI design and fabrication of the system. Other alluring features include symmetry and logarithmic diameter, which imply easy and fast algorithms for communication. Moreover, the HHC is scalable; that is it can embed HHC's of lower dimensions. The paper presents two algorithms for data communication in the HHC. The first algorithm is for one-to-one transfer, and the second is for one-to-all broadcasting. Both algorithms take O(log/sub 2/ k), where k is the total number of processors in the system. A wide class of problems, the divide & conquer class (D&Q), is shown to be easily and efficiently solvable on the HHC topology. Parallel algorithms are provided to describe how a D&Q problem can be solved efficiently on an HHC structure. The solution of a D&Q problem instance having up to k inputs requires a time complexity of O(log/sub 2/ k). >

The hierarchical hypercube: a new interconnection topology for massively parallel systems

http://staff.ustc.edu.cn/~xujm/200703.pdf

On reliability of the folded hypercubes

A new hypercube-type structure, the folded hypercube (FHC), which is basically a standard hypercube with some extra links established between its nodes, is proposed and analyzed. The hardware overhead is almost 1/n, n being the dimensionality of the hypercube, which is negligible for large n. For this new design, optimal routing algorithms are developed and proven to be remarkably more efficient than those of the conventional n-cube. For one-to-one communication, each node can reach any other node in the network in at most (n/2) hops (each hop corresponds to the traversal of a single link), as opposed to n hops in the standard hypercube. One-to-all communication (broadcasting) can also be performed in only (n/2) steps, yielding a 50% improvement in broadcasting time over that of the standard hypercube. All routing algorithms are simple and easy to implement. Correctness proofs for the algorithms are given. For the proposed architecture, communication parameters such as average distance, message traffic density, and communication time delay are derived. In addition, some fault tolerance capabilities of this architecture are quantified and compared to those of the standard cube. It is shown that this structure offers substantial improvement over existing hypercube-type networks in terms of the above-mentioned network parameters. >

Properties and performance of folded hypercubes

A scheme for global synchronization of arbitrarily large computing structures such that clock skew between any two communicating cells is bounded above by a constant is described. The scheme utilizes clock nodes that perform simple processing on clock signals to maintain a constant skew bound irrespective of the size of the computing structure. Among the salient features of the scheme is the interdependence between network topology, skew upper bound, and maximum clocking rate achievable. A 2-D mesh framework is used to present the concepts, introduce three network designs, and to prove some basic results. For each network the (constant) upper bound on clock skew between any two communicating processors, is established, and its independence of network size is shown. Simulations were carried out to verify correctness and to check the workability of the scheme. A 4*4 network was built and successfully tested for stability. Such issues as node design, clocking of nonplanar structures such as hypercubes, and the concept of fuse programmed clock networks are addressed. >

A. El-Amawy

Papers

Properties and performance of folded hypercubes

Clocking arbitrarily large computing structures under constant skew bound