Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.

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Analog circuits in ultra-deep-submicron CMOS

Due to the continuous power supply reduction, charge pumps circuits are widely used in integrated circuits (ICs) devoted to several kind of applications such as smart power, nonvolatile memories, switched capacitor circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. The main focus of this tutorial manuscript is to provide a deep understanding of the charge pumps behavior, to present useful models and key parameters and to organically and in details discuss the optimized design strategies. Finally, an overview of the main different topologies is also included.

Charge Pump Circuits: An Overview on Design Strategies and Topologies

In this paper, an optimized strategy for designing charge pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-/spl mu/m EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

Charge-pump circuits: power-consumption optimization

This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output.

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

Analog design in deep sub-micron technologies is a reality now and poses severe challenges to the circuit designer. Trends in technologies as well as circuit design are discussed. It is shown that the power required for a certain dynamic range and bandwidth decreases with minimum feature size as long as a constant ratio between signal swing and supply voltage can be maintained. Below 0.1µm channel-length, predictions of the threshold voltage endanger that requirement however. At circuit level, the problem that a low supply voltage poses on the use of switches and amplifiers is discussed. Various techniques are discussed to overcome these problems, like the use of low V th transistors, clock boosting, switched OpAmp technique, rail-to-rail input stages, back-gate driving circuits and CM level-shift techniques. Based on power estimates, the necessity of matching enhancing techniques like Auto-Zero techniques and Averaging is shown.

Analog design in deep sub-micron CMOS

This paper describes the principle and design of a CMOS Rail-to-Rail input operational amplifier with THD performance of -90 dB. The operation of the opamp is based on a standard two-stage Miller configuration and is capable of driving a low ohmic load (32 Ω). THD levels below -90 dB has not yet been shown with existing Rail-to-Rail techniques. The Rail-to-Rail functionality is achieved with a new area efficient on chip charge pump circuit for the generation of the supply voltage for the input differential pair.

http://ieeexplore.ieee.org/iel5/9916/31525/01470858.pdf

A.F. Duisters

Papers

A -90 dB THD rail-to-rail input opamp using a new local charge pump in CMOS