Japanese Journal of Applied Physicsの創刊

Multiple Valued Logic: Concepts and Representations begins with a survey of the use ofmultiple-valued logic in several modern application areas including electronic design automation algorithms and circuit design. The mathematical basis and concepts of various algebras and systems of multiple valued logic are provided including comparisons among various systems and examples of their application. The book also provides an examination of alternative representations of multiple-valued logic suitable for implementation as data structures in automated computer applications. Decision diagram structures for multiple valued applications are described in detail with particular emphasis on the recently developed quantum multiple valued decision diagram.Table of Contents: Multiple Valued Logic Applications / MVL Concepts and Algebra / Functional Representations / Reversible andQuantum Circuits / Quantum Multiple-Valued Decision Diagrams / Summary / Bibliography

Multiple-Valued Logic: Concepts and Representations

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.

Realization of multiple valued logic and memory by hybrid SETMOS architecture

In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a highly regular, redundant, and scalable design approach based on fixed-weight neural networks and multiple-valued logic are presented. It is demonstrated that the proposed design technique offers significantly improved immunity to permanent and transient faults occurring at the transistor level, and that it results in graceful degradation of circuit performance in response to device failures.

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Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors

In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics and functionality of SETs, like unrivalled integration and low power, which are complementary to the sub-20 nm CMOS, are demonstrated. Characteristics of two novel SET architectures, namely, C-SET and R-SET, aimed at logic applications are compared. Finally, it is shown that combination of CMOS and SET in hybrid ICs appears to be attractive in terms of new functionality and performance, together with better integrability for ULSI, especially because of their complementary characteristics. It is envisioned that efforts in terms of compatible fabrication processes, packaging, modeling, electrical characterization, co-design and co-simulation will be needed in the near future to achieve substantial advances in both memory and logic circuit applications based on CMOS-SET hybrid circuits.

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Few electron devices: towards hybrid CMOS-SET integrated circuits

We have developed two novel methods of fabricating very small Si single-electron transistors (SETs), called PAttern-Dependent OXidation (PADOX) and Vertical PAttern-Dependent OXidation (V-PADOX). These methods exploit special phenomena that occur when small Si structures on SiO/sub 2/ are thermally oxidized. Since the size of the resultant Si island of the SET is about 10 nm, we can observe the conductance oscillations in the SET even at room temperature. The controllability and reproducibility of these methods are excellent because of the stability of the thermal oxidation process. We are using PADOX and V-PADOX to integrate single-electron devices (SEDs)for sophisticated functions. We have fabricated and tested several kinds of memory and logic devices, This paper also describes applications of multi-input gate SETs to multiple-valued logic circuits.

A. Fujiwara

Papers

Silicon single-electron devices and their applications