Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.

Power transistor with high voltage counter implant

Impact of well structure on SE response in 90-nm bulk CMOS

An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions.

High Voltage Drain-Extended MOSFET Having Extra Drain-OD Addition

PMOS and NMOS transistors for the 0.18 μm CMOS generation with pocket punch-through stoppers are presented. A detailed study of the dose and angle of the pocket implants is presented, showing that these implant conditions do not affect the long-channel S and VT, nor the substrate current. A clear optimum is found when threshold voltage rolloff and subthreshold swing are evaluated, leading to the best performance in terms of Ion/Ioff ratio.

Study of pocket implant parameters for 0,18 um CMOS

In this paper, a design methodology for modelling and simulation of monolithic integration of low power rectifier for solid state lighting application is presented. The power conversion is built based on schottky diode fabricated in a standard BiCMOS process. The process simulation is done by using TSUPREME4 to study the doping profiles and junction depth of the standard BiCMOS fabrication steps. The modelling and design of the schottky diode for rectifier design is then made with inputs from the process simulation tool. COMSOL Multiphysics environment is used to couple both semiconductor module and circuit analysis steps. The simulated IV characteristics of the schottky diode are used to build the spice model parameters of the fabricated device. A model for monolithically integrated rectifier application and analysis is presented and analysed.

Modeling and simulation of monolithic integration of rectifiers for solid state lighting applications

Short channel devices suffer from punchthrough leakage due to barrier lowering induced by drain bias (DIBL). The device engineering strategy aims at reducing leakage from surface, sub-surface and bulk current paths. In deep sub-micron devices, bulk punchthrough is the major contributor to the DIBL leakage. This paper describes process optimization that requires some trade-offs between device parameters such as off-state current leakage, drive current and threshold voltage, to meet technology specifications. In this work we optimize well, channel, pocket and drain implant and anneal parameters to achieve the desired device characteristics.

Blanket and pocket anti punchthrough device design approaches in 0.35-/spl mu/m CMOS technology development

Bipolar transistors are well known for their high current driving capability and current gains, while CMOS transistors are dominant in the integrated circuit market because of their low power consumption and small size advantage. The combination of both types of transistor on the same chip provides a high performance circuit with a high packing density. In this work, 0.5 /spl mu/m BiCMOS technology is fully utilized to realize silicon bipolar transistors with optimized performance. Preliminary electrical results are presented on bipolar transistors fabricated for the first time in Malaysia. Significant improvements in electrical device performance can be achieved by optimizing the emitter drive-in temperature and choice of annealing system.

Fabrication and electrical characterization of silicon bipolar transistors in a 0.5-/spl mu/m based BiCMOS technology

A material system that appears to have a tremendous advantage and compatible with Si technology is the Si-SiGe system. One problem in npn SiGe HBT is boron out-diffusion from the base. Boron dopant that out-diffuses into the emitter and collector during SiGe growth and subsequent heat treatment results in the formation of parasitic energy barriers at the emitter/base and base/collector junctions. These barriers suppress the injection of electrons from the emitter to the collector which result in reduced collector current. In this work, a study on the non-linearity effects of the collector and base currents of the SiGe HBT is performed using a high performance process and device simulator SILVACO. The understanding of these effects is very important in the fabrication of high speed devices. The characteristics shows that the more out-diffusion of boron (B) at the emitter/base and base/collector junctions, the more non-ideal the currents. The underlying explanation for these trends will be discussed.

A.I.A. Rahim

Papers

Blanket and pocket anti punchthrough device design approaches in 0.35-/spl mu/m CMOS technology development

Fabrication and electrical characterization of silicon bipolar transistors in a 0.5-/spl mu/m based BiCMOS technology

A study of non-linearity effects of collector and base currents in SiGe heterojunction bipolar transistor