Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

An all-polymer semiconductor integrated device is demonstrated with a high-mobility conjugated polymer field-effect transistor (FET) driving a polymer light-emitting diode (LED) of similar size. The FET uses regioregular poly(hexylthiophene). Its performance approaches that of inorganic amorphous silicon FETs, with field-effect mobilities of 0.05 to 0.1 square centimeters per volt second and ON-OFF current ratios of >10 6 . The high mobility is attributed to the formation of extended polaron states as a result of local self-organization, in contrast to the variable-range hopping of self-localized polarons found in more disordered polymers. The FET-LED device represents a step toward all-polymer optoelectronic integrated circuits such as active-matrix polymer LED displays.

https://science.sciencemag.org/content/sci/280/5370/1741.full.pdf

Integrated Optoelectronic Devices Based on Conjugated Polymers

Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

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Nanoelectronics from the bottom up

This review article attempts to provide a comprehensive review of the recent progress in the so-called resistive random access memories (RRAMs) First, a brief introduction is presented to describe the construction and development of RRAMs, their potential for broad applications in the fields of nonvolatile memory, unconventional computing and logic devices, and the focus of research concerning RRAMs over the past decade Second, both inorganic and organic materials used in RRAMs are summarized, and their respective advantages and shortcomings are discussed Third, the important switching mechanisms are discussed in depth and are classified into ion migration, charge trapping/de-trapping, thermochemical reaction, exclusive mechanisms in inorganics, and exclusive mechanisms in organics Fourth, attention is given to the application of RRAMs for data storage, including their current performance, methods for performance enhancement, sneak-path issue and possible solutions, and demonstrations of 2-D and 3-D crossbar arrays Fifth, prospective applications of RRAMs in unconventional computing, as well as logic devices and multi-functionalization of RRAMs, are comprehensively summarized and thoroughly discussed The present review article ends with a short discussion concerning the challenges and future prospects of the RRAMs

Recent progress in resistive random access memories: Materials, switching mechanisms, and performance

We demonstrate large-scale (1 kb) high-density crossbar arrays using a Si-based memristive system. A two-terminal hysteretic resistive switch (memristive device) is formed at each crosspoint of the array and can be addressed with high yield and ON/OFF ratio. The crossbar array can be implemented as either a resistive random-access-memory (RRAM) or a write-once type memory depending on the device configuration. The demonstration of large-scale crossbar arrays with excellent reproducibility and reliability also facilitates further studies on hybrid nano/CMOS systems.

https://web.eecs.umich.edu/~wluee/Lu_JoSiCrossbar_NL2009.pdf

High-density crossbar arrays based on a Si memristive system.

It is shown that thin-film field effect transistors (FETs) made from amorphous (a-) silicon deposited by the glow-discharge technique have considerable potential as switching elements in addressable liquid crystal display panels. The fabrication of the elements and their characteristics with steady and pulsed applied potentials are discussed in some detail. Two important points are stressed: (i) a-Si device arrays can be produced by well-established photolithographic techniques, and (ii) satisfactory operation at applied voltages below 15VV is possible. Small experimental 7×5 transistor panels have been investigated and it is shown that with the present design up to 250-way multiplexing could be achieved. The reproducibility of FET characteristics is good and in tests so far no change has been observed after more than 109 switching operations.

Application of amorphous silicon field effect transistors in addressable liquid crystal display panels

We present experimental results showing that p+ amorphous silicon memory structures exhibit polarity-dependent analogue memory switching. The effect is non-volatile and we propose that it is associated with changes in a tunnelling barrier within the structure. It is also observed that conduction in the memory ON state is restricted to a narrow conducting channel through which the electrons can, under certain conditions, travel ballistically. As a conseauence, auantized resistance levels associated with ballistic electron transport are observed under certain circumstances. In the presence of a magnetic field, additional steps in the auantized resistance levels occur. A particular feature of this auantized resistance is that the effect can be observed at relatively high temperatures (up to about 190 K).

Analogue memory and ballistic electron effects in metal-amorphous silicon structures

An analogue memory device comprises a layer of doped amorphous silicon located between a first conducting layer metal contact layer of V, Co, Ni, Pd, Fe or Mn. It has been found that the selection of one of these metals as the contact exerts a significant effect on the properties of the device, e.g. the selection of Al, Au or Cu gives no switching whereas Cr, W, Ag give digital instead of analogue switching.

Amorphous silicon memory

Amorphous silicon M-p+ ni-M and M-p+ -M memory devices have been prepared. The characteristics are critically dependent on the metal used for the top contact. Devices with Cr top contacts exhibit the fast digital behaviour reported previously, whereas those using V exhibit fast analogue switching. The paper reports results for these and other metals.

Amorphous silicon analogue memory devices

A theoretical model of room temperature quantized resistance steps is described in terms of movement of a free electron Fermi surface into a quantized k -space (associated with electron confinement in real space) under the influence of applied electric field. The model is in good accordance with experimental observations such as the non-periodicity in quanta and voltage space and gives very realistic values for the parameters of electron lifetime, Fermi wavevector and geometry. Room temperature quantization is observed when the value of free electron lifetime (∼ 10 −14 s) is matched with a small size for electron confinement (∼ 7 nm or less).

A.J. Snell

Papers

Application of amorphous silicon field effect transistors in addressable liquid crystal display panels

Analogue memory and ballistic electron effects in metal-amorphous silicon structures

Amorphous silicon memory

Amorphous silicon analogue memory devices

Theory of room temperature quantized resistance effects in metal-a-Si:H-metal thin film structures