The main aim of the paper is biomedical monitoring of human being. Biomedical values are heart rate ,blood pressure ,body temperature and here we use a GPRS module and biomedical monitoring sensor and data from these sensor are updated to the web server and in addition to that we use an automated external defibrillator(AED) which automatically diagnosis the cardiac arrhythmia of ventricular fibrillation, and pulse less ventricular tachycardia and is able to deal them with an defibrillation, the requisition of electrical therapy which stops arrhythmia , allowing the heart to reestablish the normal rhythm when compare to regular defibrillator it require minimal training to use. Biomedical monitoring promises to give an overview of cardiovascular system non -invasively and this will be easy to use and operate without hospitalization.

A wearable multiparameter medical monitoring and alert system with first aid

Wireless sensor networks (WSN) are being used for huge range of applications where the traditional infrastructure based network is mostly infeasible. The most challenging aspect of WSN is that they are energy resource-constrained and that energy cannot be replenish. the wireless sensor network of power limited sensing devices called sensor deployed in a region to sense various types physical information from the environment, when these sensors sense and transmit data to other sensors present in the network, even the cluster head is elected according to check their residual energy considerable amount of energy will drain automatically to overcome this drawback by considering the protocol a fuzzy logic approach is used to elect the cluster head based on three descriptors-energy, centrality & distance and second CH is elected according to TDMA to overcome the data lost during energy drain occur in the CH .NS-2 simulation shows that proposed protocol provides higher energy efficiency. This paper proposes the mechanism or device is capable of utilizing its own system of control simply called as self-configurable clustering mechanism to detect the disordered CHs and replace them with other nodes. And results have been derived from simulator ns-2 to show the better performance.

/pdf/cluster-head-election-mechanism-based-on-fuzzy-logic-chef-2wnx6ve7af.pdf

Cluster head election mechanism-based on fuzzy logic (chef) with tdma in wsn

To design a soldier tracking system using wireless system for monitoring the parameters of soldier are as Body temperature & Temperature. Biomedical sensors: Here to find the health status of soldier we are using a body temp sensor to measure body temperature as well as pulse rate sensor. These parameters are then signal conditioned and will be stored in the memory. One of the fundamental challenges in military operations lays in that the Soldier not able to communicate with control room administrator. In addition, each organization needs to enforce certain administrative and operational work when they interact over the network owned and operated by other organizations. Thus, without careful planning and coordination, one troop cannot communicate with the troops or leverage the communication infrastructure operated by the country troops in the same region. The purpose of this investigation was to test the components of the Soldier Tracking and Performance Measurement System against the statement of requirements as found in the Request for Proposal. Secondary aims of this investigation included gathering data that will allow potential users of the system to understand its capabilities and limitations, as well as allow efficient planning of both time and resources necessary to ensure efficient and productive use of the system for training the solider.

/pdf/gsm-based-soldier-tracking-system-and-monitoring-using-8uiyrnibz3.pdf

Gsm based soldier tracking system and monitoring using wireless communication

Graphical passwords are believed to be more secure than traditional textual passwords, but the authentications are usually complex and boring for users. Furthermore, most of the existing graphical password schemes are vulnerable to spyware and shoulder surfing. A novel graphical password scheme ColorLogin is proposed in this paper. ColorLogin is implemented in an interesting game way to weaken the boring feelings of the authentication. ColorLogin uses background color, a method not previously considered, to decrease login time greatly. Multiple colors are used to confuse the peepers, while not burdening the legitimate users. Meanwhile, the scheme is resistant to shoulder surfing and intersection attack to a certain extent. Experiments illustrate the effectiveness of ColorLogin.

/pdf/authentication-scheme-for-session-passwords-using-color-and-2l5yh97c9e.pdf

Authentication scheme for session passwords using color and image

A low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using cadence virtuoso CMOS 180-nm technology, the proposed design outperforms the conventional P-FF design. The proposed design features the best power-delay-product performance in both implicit and explicit type flip flops under comparison. Counters can be designed using such flip flop. As a result power consumption is reduced compared to conventional methods. In this paper, a low power explicit pulse triggered flip flop is discussed as a proper choice of low power applications and comparison with other flip flop architectures.

/pdf/design-of-low-power-flip-flop-with-signal-feed-through-4adp42fd93.pdf

Design of Low Power Flip-Flop with Signal Feed Through Scheme for Counter Design Applications

Flip-flops are the major storage elements in all SOC's of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to the clock delays. The delay of the flip-flops should be minimized for efficient implementation. The concept of this project is to reduce the power consumption and to increase the speed and functionality of the chip. This project moves around in replacing conventional master-slave based flip flop to a pulse triggered flip flop which acts as a tribute alternate for low power applications. Initially in the critical path the pulse generation controls logic along with SVL function. A simple transistor SVL design is used to reduce the circuit complexity. In this scheme transistor sizes and pulse generation circuit can be further reduce for power saving. Here UMC CMOS 180nm technology is use in SPICE tool to design the proposed structure. This would bring up the result in power saving approximately to 38.4%. Index Terms-Flip-flop, low power,svl.

https://www.iosrjournals.org/iosr-jvlsi/papers/vol1-issue4/E0143136.pdf

A. Jagadeeswaran

Papers

Power Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic