Showing papers in "IOSR journal of VLSI and Signal Processing in 2012"

Power Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic

Abstract: Flip-flops are the major storage elements in all SOC's of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to the clock delays. The delay of the flip-flops should be minimized for efficient implementation. The concept of this project is to reduce the power consumption and to increase the speed and functionality of the chip. This project moves around in replacing conventional master-slave based flip flop to a pulse triggered flip flop which acts as a tribute alternate for low power applications. Initially in the critical path the pulse generation controls logic along with SVL function. A simple transistor SVL design is used to reduce the circuit complexity. In this scheme transistor sizes and pulse generation circuit can be further reduce for power saving. Here UMC CMOS 180nm technology is use in SPICE tool to design the proposed structure. This would bring up the result in power saving approximately to 38.4%. Index Terms-Flip-flop, low power,svl.

Image Enhancement using Ant Colony Optimization

Abstract: Applications of the Ant Colony Optimization (ACO) to solve image processing problem with a reference to a new automatic enhancement technique based on real-coded particle ant colony is proposed in this paper. The enhancement process is a non-linear optimization problem with several constraints. The objective of the proposed ACO is to maximize an objective fitness criterion in order to enhance the contrast and detail in an image by adapting the parameters of a novel extension to a local enhancement technique. The feasibility of the proposed method is demonstrated and compared with Genetic Algorithms (GAs) and Particle Swarm Optimization (PSO) based image enhancement technique. The obtained results indicate that the proposed ACO yields better results in terms of both the maximization of the number of pixels in the edges and the adopted objective evaluation. Computational time is also relatively small in the ACO case compared to the GA and PSO case.

Night Time Vehicle Detection and Classification Using Support Vector Machine

Abstract: The paper presents a vehicle detection system by locating their headlights and tail lights in the nighttime road environment. The system detects the vehicles light in front of a micro CCD camera assisted vehicle i.e. oncoming & preceding vehicles. Our system automatically controls vehicle's head lights status between low and high beams which avoids the glares for the drivers. The captured frames consist of number of bright objects over dark background. These objects are due to vehicle lamps, road reflection etc. The captured object features are used to train and classify the two classes of lights in vehicles light & other light source. The machine learning based approach, Support Vector Machine (SVM) is used to accomplish this task. The output of the SVM is simply the signed distance of the test instance from the separating hyperplane. The result show the SVM is effective to classify number of lights and it is useful for vehicle validation. Keywords - Computer vision, Driver Assistance, Image processing, Support Vector Machine, Vehicle detection.

Low Power High Speed SQRT Carry Select Adder

Abstract: Design of high speed and low power data path logic systems are one of the most challenging areas of research in VLSI system design. Adder circuit is the main building block in DSP processor. However, Digital adders suffer with the problem of carry propagation delay. To alleviate this problem Carry Select Adder (CSLA) are used in computational unit. Carry Select Adder one of the fastest adder among other. There is scope to reduce the power consumption in the regular CSLA. A simple gate level modification is required of the regular CSLA to reduce the power. This paper proposes modified 40-bit square-root CSLA (SQRT CSLA) architecture. Both the regular and modified 40-bit CSLA are designed with TSMC 0.13-µm CMOS process technology and results are compared with TSMC 0.18-µm CMOS process technology. The proposed design has reduced area and power as compared with the regular SQRT CSLA withy slight increase in the delay. The result analysis shows that proposed CSLA has better performance than conventional CSLA.

Comparative Analysis of CMOS OTA

Abstract: The Operational Transconductance amplifiers are significant building blocks for different analog circuits and systems which were previously implemented by using OPAMP. Recently, research is going on for implementing OTA circuits which will be highly linear, consumes lesser power and operate at lower supply voltage. Previous OTAs seldom worked over 200MHz whereas, the higher frequency OTA can be used as basic building block in several RF as well as microwave applications. The performance analysis of conventional OTA techniques and suggesting the topology, using advanced process technology that can break the previous frequency barrier is a key objective of this paper. Study and Analysis of different OTA topologies has been done. The appropriate topology is suggested which has a perfect balance between complexity and performance. The research includes analysis and comparison of OTA topologies from the point of view of effect of technology scaling on various performance parameters such as transconductance, supply voltage, Power consumption, dc gain, Frequency range, etc.

An Approach to Medical Image Compression Using Filters Based On Lifting Scheme

Abstract: Image compression plays an important role in the compression of medical images. Medical imagings are mainly used for diagnosis of diseases and surgical planning. Medical images are usually stored digitally. Medical Image compression plays an important role in telematics especially in telemedicine. It is necessary that medical images need to be compressed for reliability to be transmitted. In the medical image compression diagnosis is effective only when the compressed image preserves all the information of the original image. This results in a lossless compression technique. While lossy compression techniques, are more efficient in terms of storage and transmission needs but there is no warranty that they can preserve the characteristics needed in medical image processing and diagnosis. Compression plays an important role as medical imaging moves to film less imaging.CTI or MRI medical imaging are used nowadays which can produce pictures of the human body in digital form. The lifting scheme is used for the design of both orthogonal and bi-orthogonal filters .It is implemented for the orthogonal filters using two lifting steps .The performance of the proposed filters are then compared with the conventional filters in terms of compression ratio, PSNR etc. The bi-orthogonal filters are implemented using the SPIHT algorithm replacing the EZW coding for image compression. SPIHT algorithm requires fewer bits to capture the same amount of information when compared with EZW proposed.

Asynchronous FIFO Design with Gray code Pointer for High Speed AMBA AHB Compliant Memory controller

Abstract: An improved technique for FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains and asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. This method requires additional techniques to correctly synthesize and analyze the design, which are detailed in this paper. To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built-in binary ripple carry logic. This FIFO design is used to implement the AMBA AHB Compliant Memory Controller. Which means, Advanced Microcontroller Bus Architecture compliant Microcontroller .The MC is designed for system memory control with the main memory consisting of SRAM and ROM.

Parallel Hardware Implementation of Convolution using Vedic Mathematics

Abstract: Convolution is fundamental operation of most of the signal processing systems. It is necessity of time to speed up convolution process at very appreciable extent. Here Direct method of computing the discrete linear convolution of finite length sequences is used. The approach is easy to learn because of the similarities to computing the multiplication of two numbers by a pencil and paper calculation. Multipliers are basic building blocks of convolver. Since it dominates most of the execution time, for optimizing the speed, 4×4 bit Vedic multipliers based on Urdhva Tiryagbhyam sutra are used. Convolver has delay of 17.996 ns when implemented on 90 nm process technology FPGA. It also provides necessary modularity, expandability, and regularity to form different convolutions for any number of bits. The coding is done in VHDL (Very High Speed Integrated Circuits Hardware Description Language) for the FPGA , as it is being increasingly used for variety of computationally intensive applications. Simulation and synthesis is done using Xilinx 9.2i.

Core Self Evaluations and Emotional Intelligence as Correlates of Job Satisfaction among Senior Secondary School Teachers

Abstract: Job satisfaction is a sense of fulfilment that an employee derives from his job. This study investigated core self evaluations and emotional intelligence as correlates of job satisfaction among selected senior secondary school teachers in Oyo and Ogun States of Nigeria with the aim of enhancing job satisfaction in the profession. The sample consisted of three hundred participants drawn with simple random sampling technique from twelve selected schools. Six valid and reliable instruments were used for data collection; Self Esteem Scale (r = 0.86), Generalised Self Efficacy Scale (r= 0.75); Neuroticism Scale (r= 0.86); Emotional Intelligence Scale (r = 0.84); Work Locus of Control scale (r= 0.76) and Job Satisfaction Scale (r = 0.82). The administration lasted four weeks. Using correlations and multiple regression analysis, the results show that core self Evaluations and Emotional Intelligence jointly and relatively contributed to job satisfaction among secondary school teachers. On the strength of the findings, the need to foster the Core Self Evaluations and Emotional Intelligence to enhance job satisfaction was stressed and advocated.

Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAs

Abstract: Design complexity is increasing day by day in modern digital systems. Due to reconfigurable architecture, low non recurring engineering (NRE) and ease of design field programmable gate arrays (FPGA) become a better solution for managing increasing design complexity. Due to scaling trends FPGA uses more transistors which increase the leakage current. FPGAs are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. So if we are able to reduce the leakage power of an FPGA device, then it can be suitable for use in mobile as well as other low power and battery operated applications. So, this paper provides a detailed analysis of benchmark circuit 74182 a high speed carry look ahead adder by using low leakage low ground bounce noise power gating techniques. Techniques stacking power gating, Diode based stacking power gating, and Diode based staggered phase damping technique reduces peak of ground bounce noise and standby leakage current effectively. Diode based staggered phase damping technique is identified as most effective technique with 99% reduction in ground bounce noise and 75% reduction in leakage current. To evaluate the effectiveness of the power gating techniques, the simulation has been performed using BPTM 45nm technology at room temperature with supply voltage of 0.7V. To do the performance analysis we have implemented lookup table ( LUT) of benchmark circuit (74182) in Spartan-3ADSP, 90nm FPGA, Virtex-5, 65nm FPGA, Virtex-6 LP, 40nm FPGA and Kintex-7 FPGA. On comparison with conventional mode, diode based staggered phase damping technique is considered as best case power gating technique for leakage current while diode based stacking power gating technique is classified as best case power gating technique for ground bounce noise and average power with 99% reduction in ground bounce noise and 99.6% reduction in average power. All these results have been done using XILINX ISE 14.1 tool.

Design of Low Power Column bypass Multiplier using FPGA

Abstract: It is well known that multipliers consume most of the power in DSP computations. Hence, it is very important for modern DSP systems to develop low-power multipliers to reduce the power dissipation.. In this paper, we presents low power Column bypass multiplier design methodology that inserts more number of zeros in the multiplicand thereby reducing the number of switching activities as well as power consumption. The switching activity of the component used in the design depends on the input bit coefficient. This means if the input bit coefficient is zero, corresponding row or column of adders need not be activated. If multiplicand contains more zeros, higher power reduction can be achieved. To reduce the switching activity is to shut down the idle part of the circuit, which is not in operating condition. Use of look up table is an added feature to this design. Further low power adder structure reduces the switching activity. Flexibility is another critical requirement that mandates the use of programmable components like FPGAs in such devices.

A Novel Approach for High Speed and Low Power 4-Bit Multiplier

Abstract: A circuit design for a new high speed and Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different power reduction techniques. To design a multiplier it is necessary to design an AND gate and Full Adder circuit using the power reduction techniques is presented. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining computational throughput. This paper presents an accurate method of simulating the power dissipation, delay and power delay product, using different techniques in 250nm technology with supply voltage is 2.5v. The power dissipation of nearly 41% and delay 26% has been reduced by using modified proposed technique with good voltage swing levels.

Implementation and Performance Evaluation of Prefix Adders uing FPGAs

Abstract: Parallel Prefix Adders have been established as the most efficient circuits for binary addition. The binary adder is the critical element in most digital circuit designs including digital signal processors and microprocessor data path units. The final carry is generated ahead to the generation of the sum which leads extensive research focused on reduction in circuit complexity and power consumption of the adder. In VLSI implementation, parallel-prefix adders are known to have the best performance. This paper investigates four types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, spanning tree, Brent kung Adder) and compare them to the simple Ripple Carry Adder and Carry Skip Adder. These designs of varied bit-widths are simulated using model-sim simulator of 6.4 version and implemented on a Xilinx 10.1 version Spartan 3E FPGA. These fast carry-chain carry-tree adders support the bit width up to 256. We report on the area requirements and reduction in circuit complexity for a variety of classical parallel prefix adder structures. Keywords-FPGA, Prefix Adder, ALU, Xilinx, VLSI, CLA, Simulation, Synthesis

Multiple Objects Tracking using CAMshift Algorithm in Open CV

Abstract: These paper reviews tracking of multiple moving objects with CAMshift algorithm in OpenCV. In many other cases CAMshift considered a feature of tracked object which need to track in video stream. Many times CAMshift algorithm used for face tracking. But in our paper we implement approach of CAMshift algorithm which is capable of track multiple moving objects in video stream. In our paper, we have not considered any feature of object to be tracked. Here first Reference frame is selected by user and further continuously updated Binary foreground pixels are given as an argument to CAMshift, for locating location of desired objects in each frame. Motion contour detection is achieved. By providing overlap threshold criteria in scope of CAMshift algorithm multiple objects are tracked in consecutive video frames and ellipse is getting drawn around each tracked object. We proved, CAMshift algorithm can be implemented in effective manner for multiple objects tracking in video stream.

CMOS Body Driven Quaternary Logic Generator

Abstract: – This paper is about the design, simulation and study of a CMOS quaternary logic generator having a single stage CMOS body driven design. The interest of design is that the circuit consists of only one CMOS circuit, reducing the chip area and also only two supply rails is required to drive the complete circuitry. The multi-valued logic generator, designed here is also demonstrated with and without enable circuitry too. The design has been implemented with 1.8micrometer CMOS technology on Cadence virtuoso schematic Editor.

A Low Power Delay Buffer Using Gated Driver Tree

Abstract: This project presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated- clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. The simplest way to implement a delay buffer is to use shift registers. If the buffer length N is and the word-length is b , then a total of Nb DFFs are required, and it can be quite large if a standard cell for DFF is used. In addition, this approach can consume huge amount of power since on the average Nb/2 binary signals make transitions in every clock cycle. As a result, this implementation is usually used in short delay buffers, where area and power are of less concern. Although some power is indeed saved by gating the clock signal in inactive blocks, the extra R-S flip- flops still serve as loading of the clock signal and demand more than necessary clock power. We propose to replace the R-S flip-flop by a C-element and to use tree-structured clock drivers with gating so as to greatly reduce the loading on active clock drivers. Additionally, DET flip-flops are used to reduce the clock rate to half and thus also reduce the power consumption on the clock signal. The proposed ring counter with hierarchical clock gating and the control. Each block contains one C-element to control the delivery of the local clock signal "CLK" to the DET flip-flops, and only the "CKE signals along the path passing the global clock source to the local clock signal are active. The "gate" signal (CKE) can also be derived from the output of the DET flip-flops in the ring counter.

A Comparitive Approach of Spatial Domain over Frequency Domain for Image Superresolution Application

Abstract: Super-resolution aims to produce a high-resolution image from a set alone or more low-resolution images by recovering or inventing plausible high-frequency image content. Typical approach is try to reconstruct a high-resolution image using the sub-pixel displacements of several low-resolution images, usually regularized by a generic smoothness prior over the high-resolution image space. Throughout this paper, a higher resolution image is defined as an image with more resolving power. Super Resolution consists of two main steps: image registration and image reconstruction. Precise alignment of the input images is one of the important terms. In this paper, we have implemented and tested motion estimation algorithms and image reconstruction algorithms in spatial domain as well as in frequency domain in order to study their analytical parameters and a high resolution image is created by using bicubic interpolation over the prealiased images. Also the experimental as well as analytical results of this paper are successful in spatial domain as per the application of image superresolution.

Edge Enhancement and Its Applications

Abstract: We describe an automated edge enhancement procedure that operates in conjunction with clustereddot dithering, edge weighted unsharp masking, compound anisotropic diffusion etc. The goal is to make weak edges more noticeable and to give the strong edges in the half toned image a sharper and more natural appearance. Unsharp masking that is widely used for image enhancement amplifies image contrast by adding the high frequency component that is obtained by a linear high pass filter from an input image. To preserve image features, the anisotropic diffusion is governed by a local co-ordinate transformation. Experimental results show that edge enhancement is successful in improving the appearance of the text, line art and natural scenes. Also real ultrasonic images indicate effective preservation of edges and local details. Edge enhancement enhances edges in image with natural transition and sharp visual quality.

Subsampled Factor, Passband Frequency Range and Filter Order Used For Design of Oversampled Filter Bank for 2d Image Analysis

Abstract: This paper proposes an oversampled filter bank, which gives the resultant near perfect reconstruction of input image. An oversampled filter bank structure that can be implemented using popular and efficient fast filter banks to allow subband processing of an input signal with substantially reduced aliasing between subbands. For filters design direct form-II structure FIR filters are used and transformed into two dimensional forms using frequency transformation techniques. Investigation of oversampled filter bank using different oversampled factors and different filter orders for different images are carried out. The analysis of outputs of filter banks images are carried out by using peak signal to noise ratio [PSNR] of compressed images. By using local thresholding segmentation where major components of images are exposed and analysis of filter bank output images are carried out which is helpful to find the difference between images.

Face Recognition and Retrieval Using LLBP and URFB

Abstract: Face recognition is one of the major issues in biometric technology. It identifies and/or verifies a person by using a 2D/3D physical characteristics of the face images. Several techniques have been proposed for solving a major problem in face recognition such as fisher face, elastic bunch graph matching and support vector machine. However there are still many challenge problems in face recognition system such as facial expressions, pose variations occlusion and illumination change. Those variations dramatically degrade the performance of face recognition system. It is essential to build an efficient system for face recognition. We introduce a novel face representation method for face recognition integrated with URFB called Local Line Binary Pattern (LLBP) summarizes the local spatial structure of an image by thresholding the local window with binary weight and introduce the decimal number as a texture presentation .Moreover it consumes less computational cost. The basic idea of LLBP is to first obtain the binary code both along the horizontal and vertical directions separately and its magnitude, which characterizes the change in image intensity such as edges and corners, is then computed along with the unified relevance feedback(URFB) shows the advantage over traditional retrieval mechanisms. To seamlessly combine texture feature based retrieval system, a query concept-dependent fusion strategy is automatically learned. Experimental results on ORL data base consisting of 400 images show that the proposed framework is widely scalable, and effective for recognition, classification and retrieval.

Implementation of A Low Power Low Complexity VLSI Architecture for DSSS Signal Transmission and Reception

Abstract: In this paper, a new approach to design VLSI architecture for DSSS is proposed and implemented. In this we aimed towards designing a low power and low complexity architecture. An extremely lucid technique is implemented in Generating the Pseudo Random Sequence, which is the principal component in the design. The various blocks of the design like encoder, decoder, linear feedback shift register etc., are realized using low power VLSI components with an ease of low complexity approach. The Design is implemented on XA9536XL CPLD using XILINX ISE simulator and XILINX XST synthesizer. The results reveal that the power consumption, number of slice registers and other combinational circuits are less compared to the existing architectures.

Congession Avoidence in Ip Based CDMA Radio Access Network (Ran) Through Router Control

Abstract: As communication plays an important role in day to day life, the effective and efficient data transmission is to be maintained. This paper mainly deals with implements a congestion control mechanism using Router control method for IP-RAN on CDMA cellular network. The Router control mechanism uses the features of CDMA networks using active Queue Management technique to reduce delay and to minimize the correlated losses. The Random Early Detection Active Queue Management scheme (REDAQM) is to be realized for the router control for data transmission over the radio network using routers as the channel. As technology develops, we can satisfy these needs by using new tools, new applications and new personal devices. When utilizing these new personal tools and services to enrich our lives, while being mobile, we are using Mobile Multimedia applications. As new handsets, new technologies and new business models are introduced on the marketplace, new attractive multimedia services can and will be launched, fulfilling the demands. Because the number of multimedia services and even more so, the context in which the services are used is numerous, the following model is introduced in order to simplify and clarify how different services will evolve, enrich our lives and fulfill our desires.The proposed paper work is to be realized using Matlab platform.

An Area efficient and more accurate DA-based DCT with more compression rate

Abstract: In this paper, a scheme for the design of pipeline architecture for a real-time computation of the 2D DCT has been presented. The objective has been to achieve a low computation time by maximizing the operational frequency and minimizing the number of clock cycles required for the DCT computation, which, in turn, have been realized by developing a scheme for enhanced interand intra stage parallelisms for the pipeline architecture. it is most efficient to map the overall task of the DCT computation to only two pipeline stages, i.e., one for performing the task of the level-1DCT computation and the other for performing that of all the remaining decomposition levels. In view of the fact that the amount and nature of the computation performed by the two stages are the same, their internal designs ought to be the same. There are two main ideas that have been employed for the internal design of each stage in order to enhance the intra stage parallelism. The first idea is to decompose the filtering operation into two subtasks that operate independently on the evenand odd-numbered input samples, respectively. This idea stems from the fact that the DCT computation is a twosub band filtering operation, and for each consecutive decomposition level, the input data are decimated by a factor of two.

Optimized Routing Methods for VLSI Placement Design

Abstract: The VLSI placement problem is to place the objects into fixed die such that there are no overlaps among the objects and some cost metric such as wire length and routability is optimized. For this purpose A new routing method is used - called , A Deep sub-wavelength lithography, (using the 193nm lithography to print 45nm, 32nm, and possibly 22nm integrated circuits), is one of the most fundamental limitations for the continuous VLSI scaling,. Lithography printability is strongly layout dependent, thus routing plays an important role in addressing the overall circuit manufacturability and product yield since it is the last major physical design step before tape out. This paper will discuss some recent advancement of lithography friendly routing from post-routing hotspot fixing (construct by- correction) to during-routing hotspot avoidance (correct-by construction) guided by various lithography metrics.

Speech Enhancement in a Noisy Environment Using Sub-Band Processing

Abstract: One of the methods for recovering a signal corrupted by additive noise using Weiner filtering approach. This paper mainly deals with speech enhancement/recovering using Weiner filtering technique. It uses the Weighted Overlap Add filter bank implemented using digital signal processing techniques. The spectral enhancement is achieved by Voice Activity Detector in conjunction with Weiner filtering, and the results were discussed for different noise floor levels for a stationary recorded input signal.

Low-k Dielectric- A Potential Solution for Crosstalk Induced Signal Integrity issues in SWCNT Interconnects

Abstract: Crosstalk creates signal integrity issues due to capacitive coupling between adjacent interconnect wires and it is a matter of concern in high frequency interconnects. The reported work on crosstalk induced signal integrity issues in CNT interconnects till date were assuming the value of coupling capacitance as equivalent to the coupling effect between metal interconnects of same dimensions. This work tries to fill that gap; by analyzing crosstalk in bundled SWCNTs with a better model for extracting inter bundle real life coupling capacitances. This work also proposes a novel idea of reducing crosstalk effects by using low-k dielectric materials as isolation between adjacent nets. It is found that compact bundles separated by low-k dielectric can reduce crosstalk effect considerably. Keywords - Crosstalk, signal integrity, SWCNT, MWCNT, Mixed CNT

A Low Power, 8-Bit, 5MS/s Digital to Analog Converter for Successive Approximation ADC

Abstract: In this paper, a simple switched capacitor Digital to Analog Converter (DAC) is presented that exhibits monotonicity and occupies small area. The proposed DAC starts its conversion from the MSB instead of the traditional approach of starting from LSB making it suitable for use in cyclic or successive approximation analog-to-digital converters. The reference voltage is sampled once and appropriate charge is transferred to the output capacitor of the DAC. Some issues relevant to the design and their possible solutions are presented. The DAC is designed for a resolution of 8-bit. Sampling speed is chosen to be 5MS/s and the main emphasis is on low power. This DAC consumes power in the order of microwatt (����), compare with previous DACs which consumes more power, generally in the order of milliwatts. The output 8-bits along with power dissipation of 493.8 �� W has been achieved. Index Terms—DAC, Folded Cascode, SAR ADC, Transmission gates.

Design, Analysis and Simulation of High Performance Low Power 8-Bit ALU at Gate and Layout Levels

Abstract: In this work, the demand is to design an 8-bit ALU and perform analysis at gate and layout levels. The design makes use of n-Bit slice concept, the requirement is to design and develop low power high performance circuits. To achieve this, the design requires advanced styles to be employed. High level description language to be used to construct layout of 8-bit ALU and then different analyses will be carried out on this layout. Keywords - ALU, Bit Slice, Low Leakage, Threshold Volatge. I. INTRODUCTION An Arithmetic and Logic Unit (ALU) is a digital circuit that performs arithmetic and logic operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs, a single component may contain a number of ALUs. The ALU at one machine cycle executes a number of operations. During the process of operations it consumes a lot of power. Due to the power consumed by the ALU has a direct impact in the power dissipated from the processor. Hence, a design is required to implement the ALU in a fashion where the performance of the processor is improved and also the power consumed is less. This paper provides a simple design of a 8 Bit ALU for a speedy performance. This paper introduces a technique to design a ALU which consumes less power. Bit slice design is used for the construction of the 8-Bit ALU.

Performance analysis of High Speed ADC using SR F/F

Abstract: This paper present a new design of comparator for flash ADC . The flash ADC is the fastest Application ADC that requires the high speed comparator. The new design consist of sense amplifier and SR Latch ,the combining configuration of design have the considerable stable output which helps in high speed and resolution. The use of SR symmetric latch makes stable output as compared to the conventional SR latch moreover the design has high resolution. This paper has been done in 180 nm and 90nm gpdk in CADENCE VIRTUOSO. For low power application. There are many issues in the design of the comparator, we will discuss those design issues in this paper. I. Introduction The design of comparator is the most critical part in the flash ADC, since the speed and the resolution is determined by the comparator. The dual tail current sense amplifier based comparator can run faster with lower supply voltage than the normal one, and the kick back effect is also better than the normal one. The symmetric S-R latch provides shorter delay time and stable time than the normal S-R latch. Combing the sense amplifier based comparator and the symmetric S-R latch, the whole block can run faster and the output signal is more stable than the normal structure. This design of comparator is for 2GSample/sec flash ADC. Based on IEEE 802.15.3a WPAN UWB applications, the signals using multi-band orthogonal frequency division multiplexing (MB-OFDM) occupy a bandwidth of 528MHz for every band. It requires the conversion rate at least higher than 1.06GSample/sec. 1.1. The Analysis Of The Traditional Sense Amplifier Based Comparator And Sr Latch: In the analysis of any comparator there are 2 stages in which operation is divided, one is reset phase and other is regeneration phase. In this sense amplifier based comparator sense amplifier connects positive feedback with the resistive input as shown in fig.1.Now during reset phase when clock is low, the nodes of inverters (M1-M4) are charged to Vdd, through transistor M7 and M8. Again on regeneration phase when clock is high Nmos transistor M9 is turned on which is a part of differential pair M5 and M6. Current flowing through this pair controls the latch circuit and small changes between differential pair cause large output change. And this differential pair discharge the node Ni, and later difference of the input voltage will built charge it. When Ni come to Vth voltage then inverter M1,M3 turns on and this wil start the positive feedback. After Ni comes to 2Vth below Vdd transistor M2,M4 are turn on. Now with the help of strong positive feedback small input converted to full differential output. For the generation of output there is very short period of time in sense amplifier when its gain is good.so switch M11 ,M12 is added to increase the integration time. In the conventional sense amplifier, it is better to add a reset switch (M11, M12) connecting the Vdd and the Di so as to increase the integration time . In the sense amplifier there is only a very short time in which the differential pair actually have the gain. Actually the differential pair comes to triode region during Ni drop to Vth. This reset transistor also increase the active time of differential pair and decrease the offset effect in coming signals.