The computational module of several MPEG-based video encoders, which includes the known algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, is widely used to identify and compress spatial redundancy in intra (raw input) or inter (computed residue) data pixel matrices. For some modern multimedia applications, like high definition (HD H.264/AVC) or scalable (H.264/SVC) encoder solutions, the demand for fast module implementations becomes critical. Practical experiments indicate that, inside a H.264 computational module, the quantization module normally represents a real bottleneck for fast hardware implementations. Considering that we propose a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamard and Quantization with minimal communication delays. Also in this paper it is presented a practical study, considering distinct levels of parallelism for the quantization to demonstrate its influence in order to optimize global encoder complexity and performance. All proposed alternatives were designed using hardware description language VHDL and implemented into commercial FPGA boards to obtain experimental results.

Hardware integrated quantization solution for improvement of computational H.264 encoder module

The computational-intensive demands of H.264 video encoder normally imply to the use of high performance hardware solutions like dedicated multimedia DSP or programmable logic devices. These demands can be even more critical when it is necessary to implement a H.264/SVC (Scalable Video Coding) solution, an emergent encoder standard that provides the generation of flexible and adaptive multi-layer streams. The complexity of a SVC encoder increases proportionally with number of configured layers, introducing new challenges to multimedia market. In this work we propose an efficient hardware module, responsible for the transform algorithms (Hadamard and DCT) of a SVC encoder, processing up eight samples per clock. The proposed module take into account specific memory demands in order to produce an optimized solution with respect to encoder performance and complexity, aiming to reach a realizable SVC encoder.

Highly Efficient Transforms Module Solution for a H.264/SVC Encoder

Due the computational complexity of video processing algorithms the practical implementation of modern video encoders, like H.264/SVC, normally demands for some kind of hardware acceleration. In this paper we present a new integrated computational hardware module, able to perform the H.264 encoder algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization. All these hardware modules were jointly designed aiming to speed up encoder performance by optimizing timing synchronism, data handling and memory accesses. Particularly our integrated solution globally allows the complete processing of up to eight samples by clock of distinct data types (luma, blue or red chroma) for both inter or intra operations. The proposed project has been implemented for logic programmable technology using hardware description language (VHDL). Practical results obtained after synthesing and downloading the proposal into commercial FPGA boards confirms it as an innovative high performance hardware solution, adequate for real-time encoder implementation.

New integrated architecture for H.264 Transform and Quantization hardware implementation

In this paper, we propose a novel memory access reduction method to minimize the memory accesses due to weighting factors (cosine coefficients in the computation diagram of vector-radix 2D FCT pruning) and input points for implementing vector-radix 2D FCT pruning on DSP processors. The proposed method reduces the number of memory accesses in two steps: 1) Reduce the number of weighting factors and 2) Combine butterflies at two stages in vector-radix 2D FCT pruning diagram to form an efficient butterfly structure in one stage and calculate them. The proposed method is applied to implement vector-radix 2D FCT pruning on TI TMSC320C64x DSP. Experimental results show that the proposed method can achieve average of 47.2% memory access reduction, average of 58.2% clock cycle reduction and average of 20% memory space saving for weighting factors to compute vector-radix 2D fast cosine transform pruning on DSP comparing with the conventional implementation.

Memory access reduction method for efficient implementation of vector-radix 2D fast cosine transform pruning on DSP

In this paper, we propose a novel memory access reduction method to minimize the memory accesses due to weighting factors (cosine coefficients in the computation diagram of fast DCT pruning) and input points for implementing fast DCT pruning on DSP processors. The proposed method reduces the number of memory accesses in two steps: 1) Reduce the number of weighting factors and 2) Combine butterflies at two stages in fast DCT pruning diagram to form an efficient butterfly structure in one stage and calculate them. The proposed method is applied to implement Pruning FCT on TI TMSC320C64x DSP. Experimental results show that the proposed method can achieve average of 40% memory access reduction, 48.6% clock cycle reduction and 32.6% memory space saving for weighting factors to compute Pruning FCT on DSP comparing with the conventional implementation.

Memory access reduction method for efficient implementation of fast cosine transform Pruning on DSP

With continuous advancement of VLSI technology it has become possible to achieve any desired performance metric, but at a cost of increased system complexity. In this paper we present area optimal integer 2-D DCT architecture for H.264/AVC codecs. The 2-D DCT calculation is performed by utilizing the separability property, in such a way, 2-D DCT is divided into two 1-D DCT calculation that share a common memory, which considerably reduces the gate count. Due to its area optimized approach the design will find application in hand-held/mobile devices. The transform module has been coded in Verilog hardware description language (HDL) and synthesized in 0.18μ TSMC technology.

A. K. Prasoon

Papers

4 × 4 2-D DCT for H.264/AVC