Proceedings ArticleDOI
4 × 4 2-D DCT for H.264/AVC
A. K. Prasoon,K. Rajan +1 more
- pp 573-577
TLDR
This paper presents area optimal integer 2-D DCT architecture for H.264/AVC codecs, which will find application in hand-held/mobile devices due to its area optimized approach.Abstract:
With continuous advancement of VLSI technology it has become possible to achieve any desired performance metric, but at a cost of increased system complexity. In this paper we present area optimal integer 2-D DCT architecture for H.264/AVC codecs. The 2-D DCT calculation is performed by utilizing the separability property, in such a way, 2-D DCT is divided into two 1-D DCT calculation that share a common memory, which considerably reduces the gate count. Due to its area optimized approach the design will find application in hand-held/mobile devices. The transform module has been coded in Verilog hardware description language (HDL) and synthesized in 0.18μ TSMC technology.read more
Citations
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Proceedings ArticleDOI
Hardware integrated quantization solution for improvement of computational H.264 encoder module
Ronaldo Husemann,Mariano Majolo,Victor Guimaraes,Altamiro Amadeu Susin,Valter Roesler,José Valdeni de Lima +5 more
TL;DR: This paper proposes a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamard and Quantization with minimal communication delays.
Proceedings ArticleDOI
Highly Efficient Transforms Module Solution for a H.264/SVC Encoder
TL;DR: This work proposes an efficient hardware module, responsible for the transform algorithms (Hadamard and DCT) of a SVC encoder, processing up eight samples per clock, aiming to reach a realizable SVCEncoder.
Proceedings ArticleDOI
New integrated architecture for H.264 Transform and Quantization hardware implementation
TL;DR: A new integrated computational hardware module, able to perform the H.264 encoder algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, and is presented as an innovative high performance hardware solution adequate for real-time encoder implementation.
Proceedings ArticleDOI
Memory access reduction method for efficient implementation of vector-radix 2D fast cosine transform pruning on DSP
Xiangyang Liu,Yuke Wang +1 more
TL;DR: A novel memory access reduction method to minimize the memory accesses due to weighting factors and input points for implementing vector-radix 2D FCT pruning on DSP processors.
Proceedings ArticleDOI
Memory access reduction method for efficient implementation of fast cosine transform Pruning on DSP
TL;DR: A novel memory access reduction method to minimize the memory accesses due to weighting factors and input points for implementing fast DCT pruning on DSP processors.
References
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Journal ArticleDOI
Overview of the H.264/AVC video coding standard
TL;DR: An overview of the technical features of H.264/AVC is provided, profiles and applications for the standard are described, and the history of the standardization process is outlined.
Book
Introduction to data compression
TL;DR: The author explains the development of the Huffman Coding Algorithm and some of the techniques used in its implementation, as well as some of its applications, including Image Compression, which is based on the JBIG standard.
Journal ArticleDOI
Low-complexity transform and quantization in H.264/AVC
TL;DR: The 4/spl times/4 transforms in H.264 can be computed exactly in integer arithmetic, thus avoiding inverse transform mismatch problems and minimizing computational complexity, especially for low-end processors.
Journal ArticleDOI
H.264/AVC baseline profile decoder complexity analysis
TL;DR: This work study and analyze the computational complexity of a software-based H.264/AVC (advanced video codec) baseline profile decoder, determining the number of basic computational operations required by a decoder to perform the key decoding subfunctions and evaluating the dependence of the time complexity of each of the major decoder sub functions on encoder characteristics, content, resolution and bit rate.
Proceedings ArticleDOI
Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264
TL;DR: A hardware architecture for accelerating transform coding operations in MPEG-4 AVC/H.264 is presented and has been mapped into a 4 /spl times/ 4 multiple transforms unit and synthesized in TSMC 0.35um technology.