Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin s...

Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

The predictions of Moore's law are considered by experts to be valid until 2020 giving rise to "post-Moore's" technologies afterwards. Energy efficiency is one of the major challenges in high-performance computing that should be answered. Superconductor digital technology is a promising post-Moore's alternative for the development of supercomputers. In this paper, we consider operation principles of an energy-efficient superconductor logic and memory circuits with a short retrospective review of their evolution. We analyze their shortcomings in respect to computer circuits design. Possible ways of further research are outlined.

Beyond Moore's technologies: operation principles of a superconductor alternative.

Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 10^7 Josephson junctions per cm^2 is described.

Superconductor Digital Electronics: Scalability and Energy Efficiency Issues

This paper presents an overview and perspective on processing technologies required for continued scaling of leading edge and emerging semiconductor devices. We introduce the main drivers and trends affecting future semiconductor device scaling and provide examples of emerging devices and architectures that may be implemented within the next 10-20 yr. We summarize multiple active areas of research to explain how future thin film deposition, etch, and patterning technologies can enable 3D (vertical) power, performance, area, and cost scaling. Emerging and new process technologies will be required to enable improved contacts, scaled and future devices and interconnects, monolithic 3D integration, and new computing architectures. These process technologies are explained and discussed with a focus on opportunities for continued improvement and innovation.

Perspective: New process technologies required for future devices and scaling

Beyond Moore's technologies: Operation principles of a superconductor alternative

The properties of Nb/α-Si/Nb planar Josephson junctions with various degrees of doping of the amorphous silicon layer are experimentally studied. Tungsten is used as a doping impurity. The properties of the Josephson junctions are shown to change substantially when the degree of doping of the α-Si layer changes: a current transport mechanism and the shape of the current-voltage characteristic of the junctions change. Josephson junctions with SNS-type conduction are formed in the case of a fully degenerate α-Si layer. The properties of such junctions are described by a classical resistive model. Josephson junctions with a resonance mechanism of current transport through impurity centers are formed at a lower degree of doping of the α-Si layer. The high-frequency properties of such junctions are shown to change. The experimental results demonstrate that these junctions are close to SINIS-type Josephson junctions.

Properties of planar Nb/α-Si/Nb Josephson junctions with various degrees of doping of the α-Si layer

This review is devoted to a discussion of the prospects for solving the problem of a low degree of integration of the traditional elements for promising (due to the high performance and extremely low energy dissipation) superconducting digital electronics. We define three main directions on the path to compact multi-element Josephson electronic systems: (1) reduction of the Josephson junction to submicron size, (2) decrease of the area of standard logic cells, and (3) fabrication of a compact and rapid Josephson memory. We present the physical foundations of Josephson elements in order to show the fundamental constraints on establishing standard submicron tunnel contacts and compact logic cells/memory elements. This survey clearly demonstrates the essence of breakthrough technological solutions to create ultrasmall heterostructures with desired settings, reduce and optimize logic cells, and create memory unit cells based on Josephson junctions with magnetic layers.

A. L. Gudkov

Papers

Beyond Moore's technologies: Operation principles of a superconductor alternative

Properties of planar Nb/α-Si/Nb Josephson junctions with various degrees of doping of the α-Si layer

Progress in the area of new energy-efficient basic elements for superconducting electronics