A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60 to 90 % in ancilla qubits count over the existing work on reversible quantum integer multipliers.

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architectures.

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Design and analysis of efficient QCA reversible adders

We have defined a new method for automatic construction of reversible logic circuits by using the genetic programming approach. The choice of the gate library is 100% dynamic. The algorithm is capable of accepting all possible combinations of the following gate types: NOT TOFFOLI, NOT PERES, NOT CNOT TOFFOLI, NOT CNOT SWAP FREDKIN, NOT CNOT TOFFOLI SWAP FREDKIN, NOT CNOT PERES, NOT CNOT SWAP FREDKIN PERES, NOT CNOT TOFFOLI PERES and NOT CNOT TOFFOLI SWAP FREDKIN PERES. Our method produced near optimum circuits in some cases when a particular subset of gate types was used in the library. Meanwhile, in some cases, optimal circuits were produced due to the heuristic nature of the algorithm. We compared the outcomes of our method with several existing synthesis methods, and it was shown that our algorithm performed relatively well compared to the previous synthesis methods in terms of the output efficiency of the algorithm and execution time as well.

Reversible circuit synthesis by genetic programming using dynamic gate libraries

Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipationless computing and low-power computing, etc. In reversible logic there exists a one-to-one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Reversible circuits of many qubits are extremely difficult to realize; thus, reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature, researchers have proposed several designs of reversible multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and half adders for the addition of partial products increases the overhead in terms of the number of ancilla inputs and garbage outputs. This paper presents a binary tree-based design methodology for an $$N \times N$$N×N reversible multiplier. The proposed binary tree-based design methodology for $$N \times N$$N×N reversible multiplier performs the addition of partial products in parallel using the reversible ripple adders with zero ancilla bit and zero garbage bit; thereby, minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows a 17.86---60.34 % improvement in terms of ancilla inputs; and 21.43---52.17 % in terms of garbage outputs compared to all the existing reversible multiplier designs. The methodology is also extended to the design of $$N \times N$$N×N reversible signed multiplier based on modified Baugh---Wooley multiplication methodology.

Reversible logic based multiplication computing unit using binary tree data structure

Reversible logic is playing a significant role in quantum computing as quantum operations are unitary in nature. Quantum computer performs computation at an atomic level; thereby doing high performance computations beyond the limits of the conventional computing systems. Reversible arithmetic units such as adders, subtractors, multipliers form the essential component of a quantum computing system. Among the adder designs, carry look-ahead is widely used in high performance computing due to its O (log n) depth. In this work, we present improved designs of both in-place and out-of-place reversible carry look-ahead adder proposed in [1]. The proposed designs utilize the properties of the reversible Peres gate and the TR gate to optimize the logic depth, quantum cost and gate count compared to the existing designs proposed in [1]. Both the improved designs assume no input carry (C0=0). While the first approach makes use of ancilla bits to store the sum outputs, the second approach stores the sum outputs in one of the input locations.

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder

Reversible logic has gained the interest of many researchers due to its applicability in emerging low power technologies such as Quantum computing, QCA, optical computing etc, Adders/Subtractors are basic design components of any processor Optimized design of these adders results in efficient processors In this work we propose optimized Binary adders/subtractors and BCD adders The adders/subtractors designed in this work are optimized for Quantum cost and Delay We also propose a generic design of n-bit adders and subtractors In this work, we explore the use of Negative control lines for detecting overflow logic of BCD adder which considerably reduces Quantum cost, delay and gate count which result in high speed BCD adder with optimized area which give way to lot of scope in the field of reversible computing in near future

Design of optimized reversible binary adder/subtractor and BCD adder

Power dissipation has become the major concern for circuit design and implementation. Reversible Logic is the best alternative to Irreversible Logic in terms of low power consumption. Circuits designed using reversible logic have a wide array of applications. The Quantum Cost, Garbage Outputs, Ancillary Inputs and Delay are some of the parameters of reversible circuits that can be used to determine their efficiency and compare them with existing works. Optimization of these parameters are highly essential. Garbage Outputs is an important parameter that must be considered. This paper presents a design for a Reversible Radix-4 Booth Multiplier that is optimized in Garbage Cost and Ancillary inputs. The design proposed is capable of both signed and unsigned multiplication. The optimization in Garbage Cost ensures lower heat dissipation. The Encoded Booth Algorithm or Radix-4 Booth Algorithm reduces the number of partial products generated in signed multiplication to half the number generated using a Radix-2 signed multiplier making it suitable for Digital Signal Processors. The design proposed is compared to existing multiplier circuits and the parameters are tabulated.

Reversible Radix-4 booth multiplier for DSP applications

The JPEG encoder is a major component in JPEG standard which is used in image compression. It involves a complex sub-block discrete cosine transform (DCT), along with other quantization, zigzag and Entropy coding blocks. In this paper verilog design and hardware implementation of pipelined 2-D DCT along with zigzag, quantization and variable length coding is described. 2-D DCT is computed by combining two 1-D DCT that connected by a transpose buffer. The architecture uses 4059 slices 6885 LUT, 58 I/Os of Xilinx Spartan-3 XC3S1500 FPGA and works at an operating frequency of 65.55 MHz. The delay of processing each 8*8 block in an image is also evaluated to be 1.47micro seconds.

A. N. Nagamani

Papers

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits

Design of optimized reversible binary adder/subtractor and BCD adder

Reversible Radix-4 booth multiplier for DSP applications

Efficient design and FPGA implementation of JPEG encoder using verilog HDL