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Proceedings ArticleDOI

Reversible Radix-4 booth multiplier for DSP applications

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TLDR
This paper presents a design for a Reversible Radix-4 Booth Multiplier that is optimized in Garbage Cost and Ancillary inputs and is capable of both signed and unsigned multiplication.
Abstract
Power dissipation has become the major concern for circuit design and implementation. Reversible Logic is the best alternative to Irreversible Logic in terms of low power consumption. Circuits designed using reversible logic have a wide array of applications. The Quantum Cost, Garbage Outputs, Ancillary Inputs and Delay are some of the parameters of reversible circuits that can be used to determine their efficiency and compare them with existing works. Optimization of these parameters are highly essential. Garbage Outputs is an important parameter that must be considered. This paper presents a design for a Reversible Radix-4 Booth Multiplier that is optimized in Garbage Cost and Ancillary inputs. The design proposed is capable of both signed and unsigned multiplication. The optimization in Garbage Cost ensures lower heat dissipation. The Encoded Booth Algorithm or Radix-4 Booth Algorithm reduces the number of partial products generated in signed multiplication to half the number generated using a Radix-2 signed multiplier making it suitable for Digital Signal Processors. The design proposed is compared to existing multiplier circuits and the parameters are tabulated.

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Citations
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Journal ArticleDOI

Low-Cost and High-Performance 8 × 8 Booth Multiplier

TL;DR: A power/delay/area performance-improved radix-4 8 × 8 Booth multiplier with major modification for reducing delay is a parallel structure for the addition of encoded partial products to minimize multiplier’s delay.
Proceedings ArticleDOI

Design of radix 2 butterfly structure using vedic multiplier and CLA on xilinx

TL;DR: The design of butterfly structure is described using Vedic multiplier and CLA (Carry look Ahead adder) on Xilinx ISE Design suite 14.7 platform and compared the same with other technique such as with RADIX-4 booth multiplier, RCA (Ripple Carry Adder).
Journal Article

High speed Radix-4 Booth scheme in CNTFET technology for high performance parallel multipliers

TL;DR: A novel and robust scheme for radix-4 Booth scheme implemented in Carbon Nanotube Field-Effect Transistor (CNTFET) technology, which demonstrates the superiority of the proposed structure suggesting that the circuitry can be widely utilized for high speed parallel multiplier design.
Proceedings ArticleDOI

Design of garbage free reversible multiplier for low power applications

TL;DR: This work has explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation.
Proceedings ArticleDOI

Design of four point Radix-2 FFT structure on Xilinx

TL;DR: This paper consists of design of Four point Radix-2 structure that consists of complex multiplication and addition, efficient implementation of these units plays very critical role in design.
References
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Journal ArticleDOI

Irreversibility and heat generation in the computing process

TL;DR: Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
Journal ArticleDOI

Logical reversibility of computation

TL;DR: This result makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step.
Book

CMOS VLSI Design : A Circuits and Systems Perspective

TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Book

Conservative logic

TL;DR: Conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation and proves that universal computing capabilities are compatible with the reversibility and conservation constraints.
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