A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60 to 90 % in ancilla qubits count over the existing work on reversible quantum integer multipliers.

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architectures.

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Design and analysis of efficient QCA reversible adders

We have defined a new method for automatic construction of reversible logic circuits by using the genetic programming approach. The choice of the gate library is 100% dynamic. The algorithm is capable of accepting all possible combinations of the following gate types: NOT TOFFOLI, NOT PERES, NOT CNOT TOFFOLI, NOT CNOT SWAP FREDKIN, NOT CNOT TOFFOLI SWAP FREDKIN, NOT CNOT PERES, NOT CNOT SWAP FREDKIN PERES, NOT CNOT TOFFOLI PERES and NOT CNOT TOFFOLI SWAP FREDKIN PERES. Our method produced near optimum circuits in some cases when a particular subset of gate types was used in the library. Meanwhile, in some cases, optimal circuits were produced due to the heuristic nature of the algorithm. We compared the outcomes of our method with several existing synthesis methods, and it was shown that our algorithm performed relatively well compared to the previous synthesis methods in terms of the output efficiency of the algorithm and execution time as well.

Reversible circuit synthesis by genetic programming using dynamic gate libraries

Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipationless computing and low-power computing, etc. In reversible logic there exists a one-to-one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Reversible circuits of many qubits are extremely difficult to realize; thus, reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature, researchers have proposed several designs of reversible multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and half adders for the addition of partial products increases the overhead in terms of the number of ancilla inputs and garbage outputs. This paper presents a binary tree-based design methodology for an $$N \times N$$N×N reversible multiplier. The proposed binary tree-based design methodology for $$N \times N$$N×N reversible multiplier performs the addition of partial products in parallel using the reversible ripple adders with zero ancilla bit and zero garbage bit; thereby, minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows a 17.86---60.34 % improvement in terms of ancilla inputs; and 21.43---52.17 % in terms of garbage outputs compared to all the existing reversible multiplier designs. The methodology is also extended to the design of $$N \times N$$N×N reversible signed multiplier based on modified Baugh---Wooley multiplication methodology.

Reversible logic based multiplication computing unit using binary tree data structure

This paper presents an implementation of two 8-bit adders (HPA and CIA) and comparing their performance with respect to power delay product for different voltages in 90 nm regime. HPA is derived from Parallel prefix adders for minimized Power Delay product. CIA is derived from carry select adder with reduced area scheme for carry-select adders lowers this overhead by computing the carry and sum bits for a block-carry-in value of 0 only and by incrementing them afterwards depending on the final block-carry- in. For 8-bit implementation of carry generation, HPA needs 158 transistors where as CIA needs 282 transistors. HPA gives reduced power delay product compared to CIA. Tanner EDA tool is used for schematic implementation and simulating the adder designs in the 90nm technology

Design and performance evaluation of Hybrid Prefix Adder and carry increment adder in 90nm regime

Any signal processing architecture has a multiplier as its pillar. Its computational capabilities depend on the multiplier's performance. Also, low-power designs are the need of next generation processors. Reversible logic is one of the promising future low power technologies. High-speed multiplication can be achieved if the carry-propagation is faster. Digital compressors have less latency in carry-propagation. In this work, we have explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation. The proposed reversible multiplier is garbage free design and also optimized in terms of delay and quantum cost with the trade-off in ancillary inputs. The proposed multiplier finds its applications in the design of high-speed, low-power signal processing architectures such as convolution, filtering blocks, FFTs and IFTs.

Design of garbage free reversible multiplier for low power applications

Motivation for the study of technologies implementing reversible computing methods are that they offer a potential way to improve the energy efficiency of computers beyond the fundamental von Neumann-Landauer limit. Several implementations of floating-point unit in reversible logic have been suggested; and it has been found that the floating point addition is the most frequently used operation. In this paper, we present a reversible 16-bit floating-point adder that closely follows the IEEE-754 specification for binary floating-point arithmetic. The implementation of the floating-point adder using carry-lookahead adder and Brent-Kung adder structures have been designed and its performance parameters such as quantum cost, depth, garbage outputs, ancilla inputs, and delay have been compared. The proposed design has been extended to 32-bit to compare with existing works.

Design of Reversible Floating Point Adder for DSP Applications

Reversible logic has gained importance in the last few decades because of its low power dissipation. Quantum cost, garbage outputs, ancillary inputs and gate count are some of the performance parameters used to weigh reversible designs against one another. Optimization of these parameters is of great relevance to obtain an optimal design. This paper presents the design of a reversible squaring and sum-of-squares units explored for a trade-off between garbage outputs and quantum cost. The proposed work focuses on the design of dedicated unsigned and signed squaring units with a generalized methodology for n-bit squaring unit and novel sum-of-squares unit. For the optimization of the squaring circuit, the redundant product terms from the multiplier logic are eliminated. The ancillary inputs are regenerated due to which the extraneous garbage outputs are reduced. The obtained results are compared with existing state-of-art designs for performance. The garbage-cost optimized designs were found to have a 50% improvement of both ancillary inputs and garbage outputs over the direct implementation; 51% improvement of ancillary inputs and 27% improvement of quantum cost over the garbage free designs. Usage of optimized dedicated sum-of-squares unit enhances the functionality of the digital signal processor.

Design of Optimized Reversible Squaring and Sum-of-Squares Units

The widespread use of reversible logic for low-power and high-speed applications has made testing of reversible circuits a primary focus for researchers in order to ensure the manufacture of highly reliable circuits. In this work, we propose two methods to convert a given Reversible Circuit (RC) into a testable RC. Initially, we present the modification to ESOP (EXOR Sum of Product) based online testing methodology with additional test vectors to detect the wide class of faults in RC designed with k-CNOT, Fredkin and Peres gates. Then, we propose a new Design for Testability (DFT) technique which effectively detects various faults, using a minimum test set for higher fault coverage with additional DFT hardware. The proposed methodologies are validated on various reversible benchmark circuits and comparison of fault coverage and hardware overhead are compared with that of existing approaches.

A. N. Nagamani

Papers

Design and performance evaluation of Hybrid Prefix Adder and carry increment adder in 90nm regime

Design of garbage free reversible multiplier for low power applications

Design of Reversible Floating Point Adder for DSP Applications

Design of Optimized Reversible Squaring and Sum-of-Squares Units

DFT methodologies for testing k-CNOT, Fredkin and Peres based reversible circuits