The most exciting development in parallel computer architecture is the convergence of traditionally disparate approaches on a common machine structure. This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures. It then examines the design issues that are critical to all parallel architecture across the full range of modern design, covering data access, communication performance, coordination of cooperative work, and correct implementation of useful semantics. It not only describes the hardware and software techniques for addressing each of these issues but also explores how these techniques interact in the same system. Examining architecture from an application-driven perspective, it provides comprehensive discussions of parallel programming for high performance and of workload-driven evaluation, based on understanding hardware-software interactions.


* synthesizes a decade of research and development for practicing engineers, graduate students, and researchers in parallel computer architecture, system software, and applications development

* presents in-depth application case studies from computer graphics, computational science and engineering, and data mining to demonstrate sound quantitative evaluation of design trade-offs 

* describes the process of programming for performance, including both the architecture-independent and architecture-dependent aspects, with examples and case-studies

* illustrates bus-based and network-based parallel systems with case studies of more than a dozen important commercial designs

Table of Contents

1 Introduction 
2 Parallel Programs 
3 Programming for Performance 
4 Workload-Driven Evaluation 
5 Shared Memory Multiprocessors 
6 Snoop-based Multiprocessor Design 
7 Scalable Multiprocessors
8 Directory-based Cache Coherence
9 Hardware-Software Tradeoffs 
10 Interconnection Network Design 
11 Latency Tolerance 
12 Future Directions 
APPENDIX A Parallel Benchmark Suites

Parallel Computer Architecture: A Hardware/Software Approach

The overall goals and major features of the directory architecture for shared memory (Dash) are presented. The fundamental premise behind the architecture is that it is possible to build a scalable high-performance machine with a single address space and coherent caches. The Dash architecture is scalable in that it achieves linear or near-linear performance growth as the number of processors increases from a few to a few thousand. This performance results from distributing the memory among processing nodes and using a network with scalable bandwidth to connect the nodes. The architecture allows shared data to be cached, significantly reducing the latency of memory accesses and yielding higher processor utilization and higher overall performance. A distributed directory-based protocol that provides cache coherence without compromising scalability is discussed in detail. The Dash prototype machine and the corresponding software support are described. >

The Stanford Dash multiprocessor

DASH is a scalable shared-memory multiprocessor currently being developed at Stanford's Computer Systems Laboratory. The architecture consists of powerful processing nodes, each with a portion of the shared-memory, connected to a scalable interconnection network. A key feature of DASH is its distributed directory-based cache coherence protocol. Unlike traditional snoopy coherence protocols, the DASH protocol does not rely on broadcast; instead it uses point-to-point messages sent between the processors and memories to keep caches consistent. Furthermore, the DASH system does not contain any single serialization or control point. While these features provide the basis for scalability, they also force a reevaluation of many fundamental issues involved in the design of a protocol. These include the issues of correctness, performance and protocol complexity. In this paper, we present the design of the DASH coherence protocol and discuss how it addresses the above issues. We also discuss our strategy for verifying the correctness of the protocol and briefly compare our protocol to the IEEE Scalable Coherent Interface protocol.

https://www.cse.wustl.edu/~roger/569M.s09/p148-lenoski.pdf

The directory-based cache coherence protocol for the DASH multiprocessor

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

/pdf/power-minimization-in-ic-design-principles-and-applications-4l53tahw7t.pdf

Power minimization in IC design: principles and applications

Experimental evaluation

This paper presents an empirical evaluation of two memory-efficient directory methods for maintaining coherent caches in large shared memory multiprocessors. Both directory methods are modifications of a scheme proposed by Censier and Feautrier [5] that does not rely on a specific interconnection network and can be readily distributed across interleaved main memory. The schemes considered here overcome the large amount of memory required for tags in the original scheme in two different ways. In the first scheme each main memory block is sectored into sub-blocks for which the large tag overhead is shared. In the second scheme a limited number of large tags are stored in an associative cache and shared among a much larger number of main memory blocks. Simulations show that in terms of access time and network traffic both directory methods provide significant performance improvements over a memory system in which shared-writeable data is not cached. The large block sizes required for the sectored scheme, however, promotes sufficient false sharing that its performance is markedly worse than using a tag cache.

An empirical evaluation of two memory-efficient directory methods

Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. In this work, we motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multi-stage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. We show that the proposed approach allows us to make logic-level optimizations similar to the traditional multi- level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do not have any equivalent in the traditional approach. We also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that our technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of our knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

/pdf/logic-synthesis-for-large-pass-transistor-circuits-1g8wrpsh41.pdf

Logic synthesis for large pass transistor circuits

Acknowledgments.- 1 Introduction.- 1.1 Computer-Aided VLSI Design.- 1.2 The Synthesis Pipeline.- 1.3 Sequential Logic Synthesis.- 1.4 Early Work in Sequential Logic Synthesis.- 1.5 Recent Developments.- 1.5.1 State Encoding.- 1.5.2 Finite State Machine Decomposition.- 1.5.3 Sequential Don't Cares.- 1.5.4 Sequential Resynthesis at the Logic Level.- 1.6 Organization of the Book.- 2 Basic Definitions and Concepts.- 2.1 Two-Valued Logic.- 2.2 Multiple-Valued Logic.- 2.3 Multilevel Logic.- 2.4 Multiple-Valued Input, Multilevel Logic.- 2.5 Finite Automata.- 3 Encoding of Symbolic Inputs.- 3.1 Introduction.- 3.2 Input Encoding Targeting Two-Level Logic.- 3.2.1 One-Hot Coding and Multiple-Valued Minimization.- 3.2.2 Input Constraints and Face Embedding.- 3.3 Satisfying Encoding Constraints.- 3.3.1 Definitions.- 3.3.2 Column-Based Constraint Satisfaction.- 3.3.3 Row-Based Constraint Satisfaction.- 3.3.4 Constraint Satisfaction Using Dichotomies.- 3.3.5 Simulated Annealing for Constraint Satisfaction.- 3.4 Input Encoding Targeting Multilevel Logic.- 3.4.1 Kernels and Kernel Intersections.- 3.4.2 Kernels and Multiple-Valued Variables.- 3.4.3 Multiple-Valued Factorization.- 3.4.4 Size Estimation in Algebraic Decomposition.- 3.4.5 The Encoding Step.- 3.5 Conclusion.- 4 Encoding of Symbolic Outputs.- 4.1 Heuristic Output Encoding Targeting Two-Level Logic.- 4.1.1 Dominance Relations.- 4.1.2 Output Encoding by the Derivation of Dominance Relations.- 4.1.3 Heuristics to Minimize the Number of Encoding Bits.- 4.1.4 Disjunctive Relationships.- 4.1.5 Summary.- 4.2 Exact Output Encoding Targeting Two-Level Logic.- 4.2.1 Generation of Generalized Prime Implicants.- 4.2.2 Selecting a Minimum Encodeable Cover.- 4.2.3 Dominance and Disjunctive Relationships to Sat-isfy Constraints.- 4.2.4 Constructing the Optimized Cover.- 4.2.5 Correctness of the Procedure.- 4.2.6 Multiple Symbolic Outputs.- 4.2.7 The Issue of the All Zeros Code.- 4.2.8 Reduced Prime Immplicant Table Generation.- 4.2.9 Covering with Encodeability Constraints.- 4.2.10 Experimental Results Using the Exact Algorithm.- 4.2.11 Computationally Efficient Heuristic Minimization.- 4.3 Symbolic Output Don't Cares.- 4.4 Output Encoding for Multilevel Logic.- 4.5Conclusion.- 5 State Encoding.- 5.1 Heuristic State Encoding Targeting Two-Level Logic.- 5.1.1 Approximating State Encoding as Input Encoding.- 5.1.2 Constructing Input and Dominance Relations.- 5.1.3 Heuristics to Minimize the Number of Encoding Bits.- 5.1.4 Alternate Heuristic State Encoding Strategies.- 5.2 Exact State Encoding for Two-Level Logic.- 5.2.1 Generation of Generalized Prime Implicants.- 5.2.2 Selecting a Minimum Encodeable Cover.- 5.2.3 Constructing an Optimized Cover.- 5.2.4 Reduced Prime Implicant Table Generation.- 5.2.5 The Covering Step.- 5.2.6 Heuristics to Minimize the Number of Encoding Bits.- 5.2.7 Encoding Via Boolean Satisfiability.- 5.3 Symbolic Next State Don't Cares.- 5.4 State Encoding for Multilevel Logic.- 5.4.1 Introduction.- 5.4.2 Modeling Common Cube Extraction.- 5.4.3 A Fanout-Oriented Algorithm.- 5.4.4 A Fanin-Oriented Algorithm.- 5.4.5 The Embedding Algorithm.- 5.4.6 Improvements to Estimation Strategies.- 5.5 Conclusion.- 6 Finite State Machine Decomposition.- 6.1 Introduction.- 6.2 Definitions for Decomposition.- 6.3 Preserved Covers and Partitions.- 6.4 General Decomposition Using Factors.- 6.4.1 Introduction.- 6.4.2 An Example Factorization.- 6.4.3 Defining An Exact Factor.- 6.4.4 Exact Factorization.- 6.4.5 Identifying Good Factors.- 6.4.6 Limitations of the Factoring Approach.- 6.5 Exact Decomposition Procedure for a Two-Way General Topology.- 6.5.1 The Cost Function.- 6.5.2 Formulation of Optimum Decomposition.- 6.5.3 Relationship to Partition Algebra.- 6.5.4 Relationship to Factorization.- 6.5.5 Generalized Prime Implicant Generation.- 6.5.6 Encodeability of a GPI Cover.- 6.5.7 Correctness of the Exact Algorithm.- 6.5.8 Checking for Output Constraint Violations.- 6.5.9 Checking for Input Constraint Violations.- 6.5.10 Relative Complexity of Encodeability Checking.- 6.5.11 The Covering Step in Exact Decomposition.- 6.6 Targeting Arbitrary Topologies.- 6.6.1 Cascade Decompositions.- 6.6.2 Parallel Decompositions.- 6.6.3 Arbitrary Decompositions.- 6.6.4 Exactness of the Decomposition Procedure.- 6.7 Heuristic General Decomposition.- 6.7.1 Overview.- 6.7.2 Minimization of Covers and Removal of Constraint Violations.- 6.7.3 Symbolic-expand.- 6.7.4 Symbolic-reduce.- 6.8 Relationship to State Assignment.- 6.9 Experimental Results.- 6.10 Conclusion.- 7 Sequential Don't Cares.- 7.1 Introduction.- 7.2 State Minimization.- 7.2.1 Generating the Implication Table.- 7.2.2 Completely-Specified Machines.- 7.2.3 Incompletely-Specified Machines.- 7.2.4 Dealing with Exponentially-Sized Input Alphabets.- 7.3 Input Don't Care Sequences.- 7.3.1 Input Don't Care Vectors.- 7.3.2 Input Don't Care Sequences to Minimize States.- 7.3.3 Exploiting Input Don't Care Sequences.- 7.3.4 Early Work on Input Don't Care Sequences.- 7.4 Output Don't Cares to Minimize States.- 7.4.1 Exploiting Output Don't Cares.- 7.5 Single Machine Optimization at the Logic Level.- 7.5.1 Introduction.- 7.5.2 Invalid State and Unspecified Edge Don't Cares.- 7.5.3 Equivalent State Don't Cares.- 7.5.4 Boolean Relations Due To Equivalent States.- 7.5.5 Minimization With Don't Cares and Boolean Re-lations.- 7.6 Interconnected Machine Optimization at the Logic Level.- 7.6.1 Unconditional Compatibility.- 7.6.2 Conditional Compatibility.- 7.6.3 Invalid States and Edges.- 7.6.4 Searching for Unreachability and Compatibility.- 7.7 Conclusion.- 8 Conclusions and Directions for Future Work.- 8.1 Alternate Representations.- 8.2 Optimization at the Logic Level.- 8.3 Don't Cares and Testability.- 8.4 Exploiting Register-Transfer Level Information.- 8.5 Sequential Logic Synthesis Systems.

Sequential Logic Synthesis

Sketch-based user interfaces (UIs) provide a more direct and convenient way for interacting with computers, especially for performing graphical tasks. Most computer programs provide a mouse-and-palette-based UI for editing shapes, which can be cumbersome to use. In order to draw a shape, a user must first select the desired shape from a menu or from a hierarchy of menus, and then make a series of adjustments to the shape (i.e. rotation, scaling, horizontal/vertical flip, etc.). A more convenient approach to this task is to allow the user to sketch the desired shape directly and then replace it with a 'beautified' symbol with the correct transformation, all in one step. In this paper, we present a complete system for recognizing and beautifying sketched symbols. We have implemented this system as an interface to the Microsoft PowerPoint application to enable a user to sketch symbols directly onto a presentation slide.

Recognition and Beautification of Multi-Stroke Symbols in Digital Ink.

https://www.aaai.org/Papers/Symposia/Fall/2004/FS-04-06/FS04-06-013.pdf

A. Richard Newton

Papers

An empirical evaluation of two memory-efficient directory methods

Logic synthesis for large pass transistor circuits

Sequential Logic Synthesis

Recognition and Beautification of Multi-Stroke Symbols in Digital Ink.

Recognition and beautification of multi-stroke symbols in digital ink