Techniques are presented for calculating the drain current of small-geometry MOSFET's in the linear, subthreshold, and punch-through regions of device operation. The current calculation depends only on the electrostatic solution of the two-dimensional Poisson equation in the device. The accuracy of the techniques is established by comparisons with full two-dimensional simulations based on the simultaneous solution of the Poisson and minority-carrier current-continuity equations. The results of simulation also agree well with measurements on MOSFET's having submicrometer effective channel lengths. The application of the simulations to nonplanar technologies is illustrated by the analysis of a taper-isolated dynamic-gain RAM cell. A description is given of simple numerical techniques for solving Poisson's equation in the presence of nonplanar boundaries. The solution method demonstrates good convergence characteristics and minimizes computer storage requirements. Consequently, the simulation capabilities have been successfully implemented on a desktop calculator (Hewlett-Packard 9845) and on minicomputers (Hewlett-Packard 2100 and 1000-F).

Nonplanar VLSI device analysis using the solution of Poisson's equation

Design and processing concepts are presented that have led to the development of rugged high-current (100 A range) low-voltage trench DMOS transistors, featuring 4 mΩ on-resistance, with controlled bulk avalanche breakdown at 70 V and gate dielectric breakdown at 60 V. The results of a simulation-based investigation are also presented, revealing that the trench DMOS technology has at least a factor-of-two die area advantage over its planar DMOS counterpart in the range from low (50 V) to medium (200 V) voltages.

Trench DMOS transistor technology for high-current (100 A range) switching

Analytical solutions for the breakdown voltage of abrupt cylindrical and spherical junctions have been obtained, using suitable approximations for the electric field in the depletion layer. These solutions are shown to be within ±1% of exact computer solutions for doping densities of less thant 10 16 cm −1 . By normalization to the parallel plane case, these solutions have been presented in a form which allows the computation of the breakdown voltage of both cylindrical and spherical junctions using a single curve for each situation.

Analytical solutions for the breakdown voltage of abrupt cylindrical and spherical junctions

The deep-depletion breakdown voltage of silicon-dioxide/ silicon MOS capacitors is determined by the ionization-integral method, with potential distributions computed by two-dimensional relaxation techniques. Calculations cover the range of substrate doping between 1014and 1018cm-3and oxide thickness between 0.01 and 5.00 µm, providing plots of breakdown voltage versus substrate impurity concentration with oxide thickness as parameter. A universal and normalized criterion is derived for field uniformity in terms of the ratio of oxide thickness to the maximum (breakdown) width of the silicon depletion region: this ratio should be larger than 0.3 in order not to have field concentration around the edges of the metal plate.

Deep-depletion breakdown voltage of silicon-dioxide/silicon MOS capacitors

Each of a pair of complementary insulated-gate field-effect transistors is manufactured in an asymmetric lightly doped drain structure that enables the source characteristics to be decoupled from the drain characteristics. Each transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone of each transistor contains a main portion and a more lightly doped extension that meets the output channel portion. The drain extension of each transistor typically extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion of each transistor is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of lightly doped source extensions is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa. In fabricating the complementary transistor structure, the threshold body zone of each transistor is formed at the same time as the drain extension of the other transistor.

Fabrication of complementary field-effect transistors each having multi-part channel

Surface breakdown in silicon planar junctions is analysed with emphasis on the evaluation of the critical field (i.e., the maximum electric field within the depletion region at breakdown). This parameter is determined by a computer-aided experimental procedure consisting in relaxation field calculations with boundary conditions governed by junction breakdown voltage (at given gate voltage) as measured on specially processed gate-controlled diodes. The idealization (infinite doping) of the highly doped side of the junction, encountered in previous works, has been eliminated. Values of the critical field determined are in the range of 1 × 10 6 V/cm (1·0 × 10 6 V/cm for 1·0 μm gate-oxide and 1·4 × 10 6 V/cm for 0·3 μm gate-oxide). These values are substantially higher than those estimated by other authors (5–6 × 10 5 V/cm) and are consistent with independent experimental findings on avalanche (hot-carrier) injection in silicon diodes.

Surface breakdown in silicon planar junctions—A computer-aided experimental determination of the critical field

A novel uniform-field/breakdown structure is described consisting of a planar metal-overlap laterally-diffused (MOLD) Schottky diode. This structure has been demonstrated to be free of edge breakdown by numerical two-dimensional calculations. Experimentally obtained aluminum-silicon MOLD Schottky diodes have shown near-ideal characteristics in terms of breakdown voltage, reverse I–V characteristics and forward I–V characteristics. The barrier height determined from forward current measurements (zero-volts intercept and activation-energy plot) is 0.74 V.

The metal-overlap laterally-diffused (mold) Schottky diode

The avalanche injection in silicon gate-controlled diodes is analysed in terms of the physical theory of hot electrons in silicon as developed by Bartelink, Moll and Meyer. Numerically computed universal plots are given for the calculation of the hot-carrier injection ratio ηi (gate current over junction current) at given maximum interface electric field at breakdown, \mathscrE. \mathscrE=1.4×106 V/cm is experimentally determined, which is substantially higher than previously reported values. ηi≈2×10-3 is measured, in good agreement with the calculated value.

A. Rusu

Papers

Surface breakdown in silicon planar junctions—A computer-aided experimental determination of the critical field

The metal-overlap laterally-diffused (mold) Schottky diode

Avalanche Injection in Silicon Planar Semiconductor Devices