An IC process with a wide range of devices up to 1200 V is described. In addition to low-voltage bipolars and CMOS and 230-V VDMOS it provides 700-V high-side LDMOS, HV-PMOS (EPMOS) and low-voltage circuitry, low-side 1200-V LDMOS and 700-V LIGBT (lateral insulated-gate bipolar transistor), as well as 700-V interconnection. These features have been realized by using a substrate of higher resistance in a 250-300-V IC process and by adaptation in the Resurf structure for lateral DMOS. Application examples for flyback and half-bridge power conversion and as a power-bridge driver are given. >

A versatile 700-1200-V IC process for analog and switching applications

This paper establishes for the first time closed-form analytical limits from first-principle on the specific on-resistance, versus breakdown voltage with mobility compensation for all the currently known high-voltage device topologies: vertical DMOS, RESURF, super-junction, and thin-film silicon-on-insulator. The rigorous analytic treatment results in equations purely based on materials constants (relative dielectric constant), well-established fitting parameters (mobility, ionization coefficient), and natural constants (elementary charge, dielectric constant). The results are equally applicable to high-voltage diodes, bipolar devices and junction-FET, but the emphasis is on DMOS structures, which are the device of choice in many applications. Conduction-modulation devices (SCR, TRIAC, IGBT) are not considered here, as the inherent forward diode voltage renders those devices nonlinear at low anode-cathode voltage, making the term "on-resistance (Ron)" meaningless. The theory has been extended by many degrading mechanisms and real-life limitations and excellent agreement with reported results was obtained.

On the specific on-resistance of high-voltage and power devices

A process for forming both low voltage CMOS transistors and high voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well of each PMOS transistor and the n-type drain extension well of each lightly doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well of each LDD PMOS transistor.

Process for forming high and low voltage CMOS transistors on a single integrated circuit chip

The design, implementation, and modeling of high-voltage MOS transistors in a Standard CMOS technology is described. High voltage n- and p-channel transistors, with breakdown voltages of 50 and 180 V, respectively, have been fabricated. A SPICE-compatible model for these transistors is described, and its accuracy verified by comparison with experimental results.

Modeling and characterization of CMOS-compatible high-voltage device structures

A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.

Field effect transistor

A lateral 300V DMOS device is described which can be integrated in a standard bipolar IC process. The device, applicable as a high voltage source follower for analog circuits, is based upon the "double-acting resurf" principle; a modification with an interrupted p- top layer or with a stepped field plate is used. The p- layer improves the interconnection-induced breakdown and can be used in the extended drain of a 280 V PMOST.

A.W. Ludikhuize

Papers

High-voltage DMOS and PMOS in analog IC's