Comparative experiments are presented for the I/SUP 2/L properties of: method (a) a standard 25 V BV/SUB CE/ analogue process; method (b) a modification of the same process with an extra N/SUP +/ diffusion giving deeper I/SUP 2/L collectors; method (c) a modification giving a more shallow I/SUP 2/L base; and method (d) two modifications involving a selective doping of the epi layer in the I/SUP 2/L part. Aside from the additional step in each method all process parameters, as well as the I/SUP 2/L gate geometry are kept the same. It is found that processes (d) give significantly higher effective gain for the n-p-n switching transistor than the other methods. The optimum speed is also higher for these processes, but the other methods have a lower power-delay product at low current level. THe reasons for the differences are analyzed. For one of the processes (d) the effect of a shallow versus deep N/SUP +/ guard ring is discussed, and the sensitivity to variations in process parameters is commented on.

I/sup 2/L and high-voltage analog circuitry on the same chip: a comparison between various combination processes

The channel unit signal controller is a 2.56 mm/spl times/2.56 mm beam-leaded silicon integrated circuit fabricated using the complementary bipolar integrated circuit (CBIC) technology with buried injector logic (BIL). The circuit handles the distribution of signals within a channel unit of a digital telecommunications system. Several diverse circuit functions are incorporated on this device including high-speed emitter-coupled logic, lower speed buried injector logic. JFET switches, high-speed pulse amplifiers to drive the JFETs, a voltage limiter, and a comparator circuit. The channel unit signal controller is described from system and circuit points of view and the CBIC/BIL process is described.

A channel unit signal controller for shared codec D-type channel banks

This paper describes a compact model for bipolar transistors which includes a unified representation of quasi-saturation effects. The formulation of this model has been verified with results from physical simulations of a high voltage bipolar transistor. Excellent agreement between detailed physical simulations and the compact model is

A unified bipolar device

Device aspects of the epitaxial collector IIL/MTL configuration incorporating Schottky-barrier junctions (SBJ's) as output contacts (Schottky coupled IIL or Schottky coupled transistor logic) and V-grooves as lateral isolation is discussed. Typical figures for single output gates are a power-delay product of 0.10-0.18 pJ and a minimum propagation delay of 3.5-5 ns with 5- 7.5-µm design rules. Using shallow epitaxy and a reduced effective temperature of the high temperature processing steps, a 1-ns speed operation is predicted with a 4-µm feature size, thus approaching other advanced bipolar logic performances, while maintaining IIL power economy, gate density, and layouting flexibility.

Some device aspects of the epitaxial collector IIL/MTL technology

A vertically structured I2L gate, integrated with linear SBC processing, will be discussed. Previous (standard I2L) logic/linear function conflicts stemming from structural constraints have been reconciled, demonstrating second generation I2L performance with unrestrained SBC capability.

A. Yiannoulos

Papers

Buried injector logic: Second generation I 2 L performance