A system for synchronizing a multimedia content stream signal, emanating from at least one multimedia source, for play through a plurality of output devices, wherein the output devices are connected to the multimedia source by wired connections and wireless connections; the system including plural output realms, including wired realms and wireless realms; and which includes delay synchronizers and for determining a buffer delay for streaming the multimedia content stream signal from a buffer to an output device. A method of synchronizing a multimedia content stream for output to a plurality of wired and wireless output device in a network having plural realms, wherein each realm includes a CTL, includes buffering the multimedia content stream in a first realm; determining a buffer delay; transmitting the buffer delay to all CTLs in all realms of the network; and transmitting the multimedia content stream to all realms in the network.

Multimedia wired/wireless content synchronization system and method

Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

Delay locked loop circuitry for clock delay adjustment

A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

Circuitry for performing fine phase adjustment within a phase locked loop is described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The affect of the even phase signal and the odd phase signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. The weighting signals prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching. A method of performing fine phase adjustment in a phase locked loop is also described.

Method and circuitry for clock synchronization

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase

Phase interpolator device and method

A topology for a high speed voltage controlled oscillator (VCO) with quadrature outputs is produced utilizing four inverting differential circuits (12, 14, 16, 18). The fully differential four stage ring oscillator has outputs from alternate delay circuits combined in balanced exclusive OR gate frequency doublers (24, 26) to provide both in-phase and quadrature output signals at twice the ring oscillator frequency. The period of the quadrature delay signals is four gate delays and is easily realized in the Ghz frequency ranges. The in-phase and quadrature output signals are again combined in a balanced exclusive OR gate frequency doubler (36) to obtain a final output frequency quadruple the ring oscillator frequency.

Differential-logic ring oscillator with quadrature outputs

A clock recovery circuit based upon an early-late gate approach is applied to high speed serial communication links using NRZ data The circuit has no systematic phase offset and therefore requires no external phase adjustment circuits or mechanisms The circuit is used in high speed integrated receivers for applications including fiber optics, disk-drive read/write electronics, mobile communications and high rate- twisted pair data transmission in multimedia systems Quadrature samples are obtained and held which follow the shape of the NRZ data transition as a function of phase offset The data signal is passed through the limiter giving rise to a sawtooth shaped phase error signal A derivative of the error function is taken to provide a frequency error signal to provide for frequency detection and assistance in frequency acquisition of the phase lock loop circuit generating the recovered clock signal from a variably controlled oscillator

Aaron W. Buchwald

Papers

Differential-logic ring oscillator with quadrature outputs

High speed self-adjusting clock recovery circuit with frequency detection