Preface. 1. Introduction. 2. Optical Fiber. 3. Photodetectors. 4. Receiver Fundamentals. 5. Transimpledance Amplifiers. 6. Main Amplifiers. 7. Optical Transmitters. 8. Laser and Modulator Drivers. Appendix A: Eye Diagrams. Appendix B: Differential Circuits. Appendix C: S Parameters. Appendix D: Transistors and Technologies. Appendix E: Answers to the Problems. Appendix F: Notation. Appendix G: Symbols. Appendix H: Acronyms. References. Index.

Broadband Circuits for Optical Fiber Communication

Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

Delay locked loop circuitry for clock delay adjustment

Circuitry for performing fine phase adjustment within a phase locked loop is described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The affect of the even phase signal and the odd phase signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. The weighting signals prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching. A method of performing fine phase adjustment in a phase locked loop is also described.

Method and circuitry for clock synchronization

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase

Phase interpolator device and method

This paper discusses typical architectures and challenges in designing integrated circuits for data transmission over twisted-pair wire channels. To highlight the various architectural approaches, two main applications are discussed-high-bit-rate digital subscriber loop (HDSL) and fast-Ethernet. Although these two applications have orders of magnitude difference in their bit rates, they share many common building blocks including line-drivers, 24 wire hybrids, echo cancellation, digital equalization, and clock recovery. Typical integrated circuit approaches for realizing each of these blocks are presented as well as possible tradeoffs. Finally, future challenges facing integrated circuit designers are presented.

Integrated circuits for data transmission over twisted-pair channels

A topology for a high speed voltage controlled oscillator (VCO) with quadrature outputs is produced utilizing four inverting differential circuits (12, 14, 16, 18). The fully differential four stage ring oscillator has outputs from alternate delay circuits combined in balanced exclusive OR gate frequency doublers (24, 26) to provide both in-phase and quadrature output signals at twice the ring oscillator frequency. The period of the quadrature delay signals is four gate delays and is easily realized in the Ghz frequency ranges. The in-phase and quadrature output signals are again combined in a balanced exclusive OR gate frequency doubler (36) to obtain a final output frequency quadruple the ring oscillator frequency.

Differential-logic ring oscillator with quadrature outputs

Preface. Part I: System Considerations. 1. Integrated Fiber-Optic Receivers. 2. Mathematical Preliminaries. 3. Optimal Decision Theory. 4. Clock Recovery. 5. Practical High-Speed Clock Recovery. Part II: Circuit Design. 6. Heterojunction Bipolar Transistors. 7. Low-Noise Preamplifier. 8. Voltage Controlled Oscillators. 9. 6-GHz Phase=Lock Loop. 10. Clock Recovery and Data Retiming IC. Index.

Integrated fiber-optic receivers

An analog digital converter with switched-capacitor reset architecture. The analog to digital converter (ADC) includes a plurality of pipelined stages, each stage including an analog to digital converter comprising a pair of comparators outputting signals to a multiplying digital to analog converter (MDAC). The MDAC includes an opamp and a reset circuit connected to inputs of the opamp, the reset circuit including first and second capacitors and switching circuitry for precharging each of the first and second capacitors to a difference between the input and output common-mode voltages of the opamp, and during a reset phase of the MDAC, connecting the first capacitor between a positive input and a negative output of the opamp and connecting the second capacitor between a negative input and a positive output of the opamp to reset the opamp.

Kenneth W. Martin

Papers

Differential-logic ring oscillator with quadrature outputs

Integrated fiber-optic receivers

Switched-capacitor reset architecture for opamp