IEEE transactions on very large scale integration (VLSI) systems

The FFT processor is an essential part utilized for implementing the frameworks of OFDM. Due to its computational necessities, it involves large area and devours high power if implemented in hardware. In this paper, a low power and area efficient pipelined FFT processor using higher radix architecture and folding transformation is presented. The implemented low power FFT has a simple structure as that of radix 2 while utilizing the advantages of higher radix architecture. Higher radix algorithm minimizes the number of multiplication with twiddle factor which in turn reduces the large power utilization in FFT. Radix 22 multipath feedforward architecture is proposed in this paper. As various sequence are computed parallel, a high throughput can be achieved. Hardware resources needed for the presented architecture is much less than the multipath feedback architecture. Reduced chip area and lower power consumption are the merits of this FFT processor. Verilog coding for designed architecture is simulated and synthesized in Xilinx ISE Design Suite 12.1.

Fast computation of FFT in OFDM system

In this paper, we have designed an efficient CORDIC algorithm, which is used to minimize the CORDIC rotation angle with the help of several rotations. The main idea of this new CORDIC algorithm is to use an area efficient carry select adder (CSLA), instead of using a normal adder. This adder can achieve fast arithmetic operation in various data processing techniques. Finally, the comparison of various parameters like area, power and delay are calculated and they are reduced in the proposed method when compared to the existing method.

Enhanced CORDIC algorithm using an area efficient carry select adder

This paper reports the reuse of smaller optimized FFT (Fast Fourier Transform) blocks for the realization of larger power efficient radix-2 FFTs. The smaller FFT blocks use Constant Matrix Multiplication (CMM) method along its stages that are implemented with Carry Save Adders (CSA). The use of CMM at gate level enables the replacement of the multiplication operations by addition/subtractions and shifts for each stage of the real and imaginary parts of the FFT butterflies. The larger FFT is obtained through the composition of the optimized smaller FFT modules. Through a control unit, the partial decomposition of coefficients allows the computation of all coefficients necessary for the larger FFTs. The use of pipeline into the stages of the FFT enabled gains in both power and performance when compared with the previous non-pipelined solution. Moreover, the results showed that, when using pipeline, our solution is more delay and power efficient when compared with prominent works from the literature.

Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs

power design is one of the most significant challenges to maximize battery life time in portable devices and to save the energy during system process. Discrete Cosine Transform (DCT) is widely used in image and video compression process. Here in this paper, we review on low power Discrete Cosine Transform architecture by using varies methods. Discrete Cosine Transform (DCT) is most popular method used today in video compression systems. A number of algorithms have been proposed for implementation of the DCT. Loeffler (1989) has specified a new class of 1D-DCT using only 29 additions and 11 multiplications. To implement such an algorithm, one or more than one multipliers have to be integrated. This process requires a high occupation of silicon area. Arithmetic distribution is generally used for such algorithms. The coding for reconfigurable 8-point Discrete Cosine Transform (DCT) has been done using VHDL, under Xilinx platform. KeywordsCosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), Very High Speed Integrated Circuit Hardware Description Language (VHDL)

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Review Paper on Discrete Cosine Transform using Different Types of Adder

Fast Fourier Transforms have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily being memory and speed. Major problem in FFT calculation is the increased number of complex multiplication units. Folding transformations are used to design FFT architectures with reduced number of functional units. In the folding transformation, many butterflies in the same column can be mapped to one butterfly unit. A highly efficient pipelined folded FFT architecture for 8 point R2 FFT is presented here. When compared with the normal R2 FFT architecture, the pipelined architecture shows efficiency both in speed and area consumption. Futher reduction in the area can be obtained by using COordinate Rotation for DIgital Computer (CORDIC) algorithm, which is an add and shift algorithm that replaces complex twiddle factor multiplication. The FFT block is designed to be capable of computing 8 point FFT and employs R2 (Radix2) architecture which is simple, elegant and best suited for communication applications. VHDL coding is simulated and synthesized in Xilinx ISE Design Suite 12.1.

An efficient folded pipelined architecture for Fast Fourier Transform using Cordic algorithm

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Design of Efficient Fast Fourier Transform

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Abhila R Krishna

Papers

An efficient folded pipelined architecture for Fast Fourier Transform using Cordic algorithm

Design of Efficient Fast Fourier Transform

Design of Memory Efficient Architecture for Mul-tilevel Discrete Wavelet Transform