Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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Multi-core Devices for Safety-critical Systems: A Survey

Towards mixed criticality task scheduling in cyber physical systems: Challenges and perspectives

The mixed-criticality system provides multiple real-time applications with different criticalities in a single system. Poor energy-saving performance of the previous studies on mixed-criticality sporadic tasks are mainly due to the fact that the slack time generated from the random arrival of sporadic tasks is not taken into account. In this article, we focus on scheduling energy aware mixed-criticality sporadic tasks and take the random arrival of sporadic tasks into account. We proposed a dynamically frequency updating mixed-criticality algorithm (DFU). DFU based on the earliest deadline first scheme can exploit the slack time generated from high criticality tasks in a low criticality mode to reduce processor frequency. In addition, it also can dynamically update the utilization of sporadic tasks set to further reduce processor frequency. The simulation experiments are conducted to evaluate the performance of DFU and experimental results show that DFU consumes 34.29% less energy than that of the existing algorithms.

Energy-Aware Mixed-criticality Sporadic Task Scheduling Algorithm

The static resource allocation in time-triggered systems offers significant benefits for the safety arguments of dependable systems. However, adaptation is a key factor for energy efficiency and fault recovery in Cyber-Physical System (CPS). This paper introduces the Adaptive Time-Triggered Multi-Core Architecture (ATMA), which supports adaptation using multi-schedule graphs while preserving the key properties of time-triggered systems including implicit synchronization, temporal predictability and avoidance of resource conflicts. ATMA is an overall architecture for safety-critical CPS based on a network-on-a-chip with building blocks for context agreement and adaptation. Context information is established in a globally consistent manner, providing the foundation for the temporally aligned switching of schedules in the network interfaces. A meta-scheduling algorithm computes schedule graphs and avoids state explosion with reconvergence horizons for events. For each tile, the relevant part of the schedule graph is efficiently stored using difference encodings and interpreted by the adaptation logic. The architecture was evaluated using an FPGA-based implementation and example scenarios employing adaptation for improved energy efficiency. The evaluation demonstrated the benefits of adaptation while showing the overhead and the trade-off between the degree of adaptation and the memory consumption for multi-schedule graphs.

Adaptive Time-Triggered Multi-Core Architecture

Network-on-chip (NoC) has emerged as a scalable on-chip communication platform and, hence, has become more popular. However, as the sole communication medium, a single point of failure raised by any permanent fault can cause the failure of the entire system. Subsequently, the NoC has become a critically exposed unit that must be protected. This article primarily presents a test-time-independent and optimally distributed test scheme named “Dugdugi” that addresses channel faults, e.g., short in an Octagon and similar NoC architectures to achieve high reliability. The proposed scheme is extended to cover other channel faults, such as stuck-at and transient faults, to give its impression of a comprehensive approach. Experimental results show that the proposed scheme incurs little hardware area and detects all modeled short faults by a few clocks with achieving fault coverage metric up to 100%. Online evaluation reveals the effect of channel-short faults on various network performance metrics. In comparison to prior methodologies, the proposed scheme improves hardware area overhead up to 71.79% and reduces test time over 94.20%. Furthermore, performance overhead, such as packet latency and energy consumption, reduces up to 40.85% and 43.87%, respectively.

Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

We observe a tremendous trend towards mixed-criticality systems, where subsystems of different safety assurance level coexist and interact. In addition, embedded systems are demanded to be efficient in terms of energy consumption to achieve longer operation time with the same battery capacity. This paper introduces a novel architecture for an adaptive time-triggered communication at the chip-level, which addresses the above challenges. In the proposed architecture, time-triggered communication offers safety by establishing temporal and spatial segregation of the communication channels. In addition, adaptivity enables the communication backbone to adapt the injection time of message according to the real execution time of computational tasks, thereby decreasing the overall makespan of the application and increasing the sleep time. In addition to power saving, adaptivity helps to achieve fault recovery, as a faulty subsystem can be shut down and replaced by a backup subsystem. The proposed concept has been evaluated by an example scenario. The results exhibit that using the proposed concept, makespan of the processor and consequently the energy consumption are reduced. In addition to energy, the amount of the used memory for storing the communication schedules is also decreased.

Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-Chips

In this paper we present a new fault model for testing bus components using their functionality. With the aim of a new fault model definition all components in a bus except cores of the SoC will be tested as fast as possible. According to the proposed method in this paper, at first, wires and small components will be tested by marching test patterns as the test data and, after that based on a proposed method; the new format faults for the bus will be used. Using AMBA-AHB as the experimental result, the new fault model shows efficiency in comparison with corresponding stuck-at.

Functional fault model definition for bus testing

The increasing trend towards mixed-critical systems, in which applications with different levels of criticality coexist and interact on the same platform, calls for fault-tolerant hardware platforms. On the other hand, due to the demanded performance in such systems, network-on-chips are employed to interconnect several computation resources. Consequently, the detection and localization of faults in the communication and computation resources becomes a challenge, if a high number of shared resources (e.g., routers, physical links) are used. This paper proposes a new hardware architecture for run-time fault detection and localization in mixed-criticality networks-on-chips. The proposed architecture detects the transient and permanent faults in the network and distinguishes between faults of different resources. The fault detection and localization mechanisms have been evaluated using Gem5 simulation and example scenarios.

Adele Maleki

Papers

Adaptive Time-Triggered Multi-Core Architecture

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-Chips

Functional fault model definition for bus testing

Fault Detection and Localization for Network-on-Chips in Mixed-Criticality Systems