Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy.As a result you will be able to design and emulate the entire memory hierarchy. . Understand all levels of the system hierarchy -Xcache, DRAM, and disk. . Evaluate the system-level effects of all design choices. . Model performance and energy consumption for each component in the memory hierarchy.

Memory Systems: Cache, DRAM, Disk

Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. The performance of a given cache architecture is largely determined by the behavior of the application using that cache. Desktop systems have to accommodate a very wide range of applications and therefore the manufacturer usually sets the cache architecture as a compromise given current applications, technology and cost. Unlike desktop systems, embedded systems are designed to run a small range of well-defined applications. In this context, a cache architecture that is tuned for that narrow range of applications can have both increased performance as well as lower energy consumption. We introduce a novel cache architecture intended for embedded microprocessor platforms. The cache can be configured by software to be direct-mapped, two-way, or four-way set associative, using a technique we call way concatenation, having very little size or performance overhead. We show that the proposed cache architecture reduces energy caused by dynamic power compared to a way-shutdown cache. Furthermore, we extend the cache architecture to also support a way shutdown method designed to reduce the energy from static power that is increasing in importance in newer CMOS technologies. Our study of 23 programs drawn from Powerstone, MediaBench and Spec2000 show that tuning the cache's configuration saves energy for every program compared to conventional four-way set-associative as well as direct mapped caches, with average savings of 40% compared to a four-way conventional cache.

/pdf/a-highly-configurable-cache-architecture-for-embedded-9ep56q7ix5.pdf

A highly configurable cache architecture for embedded systems

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

In this work, we provide a technique for efficiently exploring a parameterized system-on-a-chip (SoC) architecture to find all Pareto-optimal configurations in a multi-objective design space. Globally, our approach uses a parameter dependency model of our target parameterized SoC architecture to extensively prune non-optimal sub-spaces. Locally, our approach applies Genetic Algorithms (GAs) to discover Pareto-optimal configurations within the remaining design points. The computed Pareto-optimal configurations will represent the range of performance (e.g., timing and power) tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the parameterized SoC architecture. We have successfully applied our technique to explore Pareto-optimal configurations for a number of applications mapped on a parameterized SoC architecture.

/pdf/multi-objective-design-space-exploration-using-genetic-496nqhsddu.pdf

Multi-objective design space exploration using genetic algorithms

As the age of Big Data emerges, it becomes necessary to take the five dimensions of Big Data - volume, variety, velocity, volatility and veracity - and focus these dimensions towards one critical emphasis - value.The Encyclopedia of Business Analytics and Optimization confronts the challenges of information retrieval in the age of Big Data by exploring recent advances in the areas of knowledge management, data visualisation, interdisciplinary communication and others. Through its critical approach and practical application, this book will be a must-have reference for any professional, leader, analyst or manager interested in making the most of the knowledge resources at their disposal.

Encyclopedia of Business Analytics and Optimization

Advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the devices components. The M7CORE M3 architecture was developed specifically for these embedded applications. To address the growing need for longer battery life and higher performance, an 8-Kbyte, 4-way set-associative, unified (instruction and data) cache with pro-grammable features was added to the M3 core. These features allow the architecture to be optimized based on the applications requirements. In this paper, we focus on the features of the M340 cache sub-system and illustrate the effect on power and perfor-mance through benchmark analysis and actual silicon measure-ments.

/pdf/a-low-power-unified-cache-architecture-providing-power-and-4ibsmqj9rj.pdf

A low power unified cache architecture providing power and performance flexibility (poster session)

A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12,14), determining access permissions (86), providing state information (60), determining access permissions (86) based on the access request (84), and selectively modifying the access permissions based on the state information (90). The state information (60) may relate to debug operation, operation from unsecure or unverified memories, memory programming, direct memory access operation, boot operation, software security verification, security levels, security monitor operation, operating mode, fault monitor, external bus interface, etc (88).

Method and apparatus for determining access permission

A memory controller (32) and method thereof configures a prefetch buffer (30) dynamically for interfacing between multiple bus masters (12, 14, 16) of different burst support and multiple memories having different characteristics. A line size of at least a portion of the prefetch buffer (30) is modified based upon the memory controller receiving a read request from one of the bus masters (12, 14, 16). An adaptive method to optimally replace prefetch buffer lines uses prioritized status (status) field information to determine which buffer line to replace.

Method and apparatus for dynamic prefetch buffer configuration and replacement

In one embodiment, a data processing system (10) includes a first master, storage circuitry (35) coupled to the first master (12) for use by the first master (12), a first control storage circuit (38) which stores a first prefetch limit (60), a prefetch buffer (42), and prefetch circuitry (40) coupled to the first control storage circuit, to the prefetch buffer, and to the storage circuitry. In one embodiment, the prefetch circuitry (40) selectively prefetches a predetermined number of lines from the storage circuitry into the prefetch buffer (42) based on whether or not a prefetch counter, initially set to a value indicated by the first prefetch limit, has expired. In one embodiment, the first prefetch limit may therefore be used to control how many prefetches occur between misses in the prefetch buffer.

Prefetch control in a data processing system

Advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the device’s components. The M•CORE M3 architecture was developed specifically for these embedded applications. To address the growing need for longer battery life and higher performance, an 8Kbyte, 4-way setassociative, unified (instruction and data) cache with programmable features was added to the M3 core. These features include write mode selection, way management, and buffer enabling/disabling which allow the architecture to be optimized based on the application’s requirements. In this paper, we present the features of the unified cache architecture and illustrate the effect on power and performance through benchmark analysis and actual silicon measurements. A Programmable Unified Cache Architecture for Embedded Applications

Afzal M. Malik

Papers

A low power unified cache architecture providing power and performance flexibility (poster session)

Method and apparatus for determining access permission

Method and apparatus for dynamic prefetch buffer configuration and replacement

Prefetch control in a data processing system

A programmable unified cache architecture for embedded applications