This paper describes a variety of fault and error models which are used as the basis for designing fault-tolerant Very Large Scale Integrated (VLSI) systems. The fault models describe physical defects and failures and the input patterns which will expose them, and are suitable for testing, while error models describe the effects on the functional outputs of defects and are useful for on-line error detection. The models are described at various levels of abstraction. The differences between fault and error models for identical functional modules are also illustrated.

Fault and error models for VLSI

Due to the evolution of technology constraints, especially energy constraints which may lead to heterogeneous multi-cores, and the increasing number of defects, the design of defect-tolerant accelerators for heterogeneous multi-cores may become a major micro-architecture research issue. Most custom circuits are highly defect sensitive, a single transistor can wreck such circuits. On the contrary, artificial neural networks (ANNs) are inherently error tolerant algorithms. And the emergence of high-performance applications implementing recognition and mining tasks, for which competitive ANN-based algorithms exist, drastically expands the potential application scope of a hardware ANN accelerator. However, while the error tolerance of ANN algorithms is well documented, there are few in-depth attempts at demonstrating that an actual hardware ANN would be tolerant to faulty transistors. Most fault models are abstract and cannot demonstrate that the error tolerance of ANN algorithms can be translated into the defect tolerance of hardware ANN accelerators. In this article, we introduce a hardware ANN geared towards defect tolerance and energy efficiency, by spatially expanding the ANN. In order to precisely assess the defect tolerance capability of this hardware ANN, we introduce defects at the level of transistors, and then assess the impact of such defects on the hardware ANN functional behavior. We empirically show that the conceptual error tolerance of neural networks does translate into the defect tolerance of hardware neural networks, paving the way for their introduction in heterogeneous multi-cores as intrinsically defect-tolerant and energy-efficient accelerators.

http://pages.saclay.inria.fr/olivier.temam/files/eval/T12.pdf

A defect-tolerant accelerator for emerging high-performance applications

Computer Aids For VLSI Design

The COSMOS symbolic fault simulator generates test sets for combinational and sequential MOS circuits represented at the switch level. All aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values are captured. To generate tests for a circuit, the program derives Boolean functions representing the behavior of the good and faulty circuits over a sequence of symbolic input patterns. It then determines a set of assignments to the input variables that will detect all faults. Symbolic simulation provides a natural framework for the user to supply an overall test strategy, letting the program determine the detailed conditions to detect a set of faults. Symbolic preprocessing of switch-level networks, combined with efficient Boolean manipulation makes this approach feasible.

/pdf/test-pattern-generation-for-sequential-mos-circuits-by-14c869ujvo.pdf

Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation

A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.

Methods for the modeling and fault simulation of complementary metal oxide semiconductor circuits

An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

Agrawal

Papers

Modeling and Test Generation Algorithms for MOS Circuits