The paper surveys a decade of R&D on coarse grain reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of computing science, and advocates the introduction of a new soft machine paradigm to replace CAD by compilation.

A decade of reconfigurable computing: a visionary retrospective

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

A one-of-a-kind survey of the field of Reconfigurable Computing Gives a comprehensive introduction to a discipline that offers a 10X-100X acceleration of algorithms over microprocessors Discusses the impact of reconfigurable hardware on a wide range of applications: signal and image processing, network security, bioinformatics, and supercomputing Includes the history of the field as well as recent advances Includes an extensive bibliography of primary sources

Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays

The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements

Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems. Consequently, engineers strive to create ever smaller and faster products, many of which have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems. This article presents an overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption.

/pdf/an-overview-of-reconfigurable-hardware-in-embedded-systems-4frwnpe71b.pdf

An overview of reconfigurable hardware in embedded systems

The evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. The system designers are faced with a challenging set of problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper presents first the major challenges in realizing flexible microelectronic system solutions for future mobile communication applications. Based thereupon, the architecture design of flexible system-on-a-chip solutions in the digital baseband processing for future mobile radio devices is discussed. The focus of the paper is the introduction of a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.

Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems

The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future broadband mobile communication systems. Here, new and flexible microelectronic architectures are required solving various problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper sketches first the major motivation for developing flexible microelectronic System-onChip (SoC) solutions for the digital baseband processing in future mobile radio devices. The paper introduces a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. The focus of this contribution is the efficient communication and dynamic reconfiguration realization for such reconfigurable array architectures, which is crucial for their overall performance and flexibility.

Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures.

The evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. The system designers are faced with a challenging set of problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper presents first the major challenges in realizing flexible microelectronic system solutions for digital baseband signal processing in future mobile communication applications. Based thereupon, the architecture design of flexible system-on-a-chip solutions is discussed. The focus of the paper is the introduction of a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.

A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing

Alsolaim, Ahmad Mohammed. Ph.D. Aug. 2002 Electrical Engineering and Computer Science Dynamically reconfigurable architecture for third peneration mobile svstems (309 pp.) Director of Dissertation: Professor Janusz Starzyk A third generation mobile system is scheduled for launch in 2002. The system provides a high data rate tha t can be used for multimedia and internet services. As the diversity of required services and performance of the mobile units increases, the traditional hardware implementation of the mobile terminal will fall short of providing the required flexibility and performance. This justifies the use of reconfigurable hardware. The typical implementations of the current mobile systems a re a mixture of ASICs and DSPs. ASICs are used for their high performance and low power. DSPs are used for their flexibility. The two implementation paradigms are combined in this research to reach a compromise between low cost, low power consumption (long battery life), flexibility, and performance. A dynamically reconfigurable computing architecture is a n ideal implementation solution for the third and future generations of mobile systems. This dissertation delineates the design and simulation of a new dynamically reconfigurable architecture called DRAW. DRAW is a hardware fabric specially designed for the third generation wireless mobile systems.

Dynamically reconfigurable architecture for third generation mobile systems

The focus of the paper is a parallel and dynamically reconfigurable hardware architecture tailored to wireless mobile handsets. Its performance issues and potential are discussed. The paper presents the major challenges in realizing a flexible microelectronic system for mobile communication applications. The architecture design of flexible system-on-a-chip solutions in the digital baseband processing for mobile radio devices are also discussed.

Ahmad Alsolaim

Papers

Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems

Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures.

A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing

Dynamically reconfigurable architecture for third generation mobile systems

Dynamically reconfigurable solution in the digital baseband processing for future mobile radio devices