Despite the perception people may have regarding the agricultural process, the reality is that today's agriculture industry is data-centered, precise, and smarter than ever. The rapid emergence of the Internet-of-Things (IoT) based technologies redesigned almost every industry including “smart agriculture” which moved the industry from statistical to quantitative approaches. Such revolutionary changes are shaking the existing agriculture methods and creating new opportunities along a range of challenges. This article highlights the potential of wireless sensors and IoT in agriculture, as well as the challenges expected to be faced when integrating this technology with the traditional farming practices. IoT devices and communication techniques associated with wireless sensors encountered in agriculture applications are analyzed in detail. What sensors are available for specific agriculture application, like soil preparation, crop status, irrigation, insect and pest detection are listed. How this technology helping the growers throughout the crop stages, from sowing until harvesting, packing and transportation is explained. Furthermore, the use of unmanned aerial vehicles for crop surveillance and other favorable applications such as optimizing crop yield is considered in this article. State-of-the-art IoT-based architectures and platforms used in agriculture are also highlighted wherever suitable. Finally, based on this thorough review, we identify current and future trends of IoT in agriculture and highlight potential research challenges.

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Internet-of-Things (IoT)-Based Smart Agriculture: Toward Making the Fields Talk

Viable cryptosystem designs must address power analysis attacks, and masking is a commonly proposed technique for defending against these side-channel attacks It is possible to overcome simple masking by using higher-order techniques, but apparently only at some cost in terms of generality, number of required samples from the device being attacked, and computational complexity We make progress towards ascertaining the significance of these costs by exploring a couple of attacks that attempt to efficiently employ second-order techniques to overcome masking In particular, we consider two variants of second-order differential power analysis: Zero-Offset 2DPA and FFT 2DPA

Towards efficient second-order power analysis

Arbiter Physically Unclonable Functions (APUFs), while being relatively lightweight, are extremely vulnerable to modeling attacks. Hence, various compositions of APUFs such as XOR APUF and Lightweight Secure PUF have been proposed to be secure alternatives. Previous research has demonstrated that PUF compositions have two major challenges to overcome: vulnerability against modeling and statistical attacks, and lack of reliability. In this paper, we introduce a multiplexer-based composition of APUFs, denoted as MPUF, to simultaneously overcome these challenges. In addition to the basic MPUF design, we propose two MPUF variants namely cMPUF and rMPUF to improve the robustness against cryptanalysis and reliability-based modeling attack, respectively. An rMPUF demonstrates enhanced robustness against the reliability-based modeling attack, while even the well-known XOR APUF, otherwise robust to machine learning based modeling attacks, has been modeled using the same technique with linear data and time complexities. The rMPUF can provide a good trade-off between security and hardware overhead while maintaining a significantly higher reliability level than any practical XOR APUF instance. Moreover, MPUF variants are the first APUF compositions, to the best of our knowledge, that can achieve Strict Avalanche Criterion without using any additional input network (or hardware) for challenge transformation. Finally, we validate our theoretical findings using Matlab-based simulations of MPUFs.

A Multiplexer-Based Arbiter PUF Composition with Enhanced Reliability and Security

This is an implementation of the Data Encryption Standard (DES) for the open-source computer software system, Sage. This only allows the encryption of a single 64-bit plaintext with a 64-bit key. It thus provides a foundation for the user to build up triple-DES, DES in standard NIST block modes (ECB, CBC etc), and for padding. None of these are provided in this implementation.

Data Encryption Standard (DES) for Sage

Evoked by the increasing need to integrate side-channel countermeasures into security-enabled commercial devices, evaluation labs are seeking a standard approach that enables a fast, reliable and robust evaluation of the side-channel vulnerability of the given products. To this end, standardization bodies such as NIST intend to establish a leakage assessment methodology fulfilling these demands. One of such proposals is the Welch’s t test, which is being put forward by Cryptography Research Inc. and is able to relax the dependency between the evaluations and the device’s underlying architecture. In this work, we deeply study the theoretical background of the test’s different flavors and present a roadmap which can be followed by the evaluation labs to efficiently and correctly conduct the tests. More precisely, we express a stable, robust and efficient way to perform the tests at higher orders. Further, we extend the test to multivariate settings and provide details on how to efficiently and rapidly carry out such a multivariate higher-order test. Including a suggested methodology to collect the traces for these tests, we point out practical case studies where different types of t tests can exhibit the leakage of supposedly secure designs.

Leakage assessment methodology: Extended version

A new cryptographic standard FPGA board SAKURA-G equipped with a 45-nm Xilinx Spartan-6 was developed to evaluate the security of cryptographic circuits against physical attacks and to measure the hardware performance of encryption algorithms. In addition to its rich array of capabilities, improved power analysis functionality over previous standard boards SASEBO-GII and SASEBO-G is demonstrated thorough CPA (Correlation Power Analysis) on an AES circuit.

Side-channel AttacK User Reference Architecture board SAKURA-G

In this study, the properties of physical unclonable functions (PUFs) for 28-nm process field-programmable gate arrays (FPGAs) are examined. A PUF is a circuit that generates device-specific IDs by extracting device variations. Owing to device variation, no two PUFs will generate the same ID even if they have identical structures and are manufactured on the same silicon wafer. However, because the influence of device variation increases as the size of the process node shrinks, it is uncertain whether PUFs can be built using recently developed small-scale process nodes, even though the technology of variation control is constantly advancing. While many PUFs using 40-nm or larger process nodes have been reported, smaller devices have not yet been studied to the authors’ knowledge, and this is the first published journal article on PUFs for 28-nm process FPGAs. In this paper, within-die reproducibility, die-to-die uniqueness, and other properties are evaluated, and the feasibility of PUFs on 28-nm FPGAs is discussed.

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays

A physical unclonable function (PUF) device, and a PUF reader which extracts PUF parameters required to calculate a response output from a challenge input by analyzing an operation of the PUF device. Operation parameters characterizing an operation state are obtained by observing a power waveform, an electromagnetic waveform, or a processing time of the PUF device at that time. Authentication of the PUF device is based on the extracted parameters. The PUF reader executes authenticity determination as to whether or not the PUF device is a valid PUF device by monitoring an operation of the PUF device during response generation based on the operation parameters.

Authentication processing method and apparatus

The disclosed authentication processing device (1) identifies a mimic device while using a PUF circuit of a simple configuration; (2) does not decrease processing capability of the PUF circuit; (3) without using ECC, determines certainty; (4) performs authentication locally; and (5) does not have a limit in the number of times of use. The disclosed authentication processing device is provided with a PUF device and a PUF reader for analyzing the operation of the PUF device, extracting from a challenge input a PUF parameter required for calculating a response output, observing a power waveform, an electromagnetic waveform, or processing time of the PUF device at that time and extracting operation parameters characterizing the operational state thereof, and authenticating the PUF device on the basis of each of the extracted parameters. The PUF reader observes the operation during response generation of the PUF device and performs authenticity assessment of whether the PUF device is legitimate on the basis of the operation parameters.

Authentication processing method and device

We developed a compact sensor module for hydroponics that measures the nutrient concentration and water level using simple oscillator circuits. Oscillation frequencies are measured and are found to change in response to the resistance and capacitance between metal wires on a printed circuit board submerged in liquid fertilizer. A microprocessor is mounted on the sensor board for measurement and communication. Expressions relating the oscillating frequencies, liquid fertilizer concentration, water level and temperature were derived through experiments using the sensor module.

Akashi Satoh

Papers

Side-channel AttacK User Reference Architecture board SAKURA-G

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays

Authentication processing method and apparatus

Authentication processing method and device

A compact hardware design of a sensor module for hydroponics