Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.

Semiconductor device and method of fabricating semiconductor device with high CMP uniformity and resistance to loss that occurs in dicing

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Electronic devices and systems, and methods for making and using the same

Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.

Methods and systems for determining a position of inspection data in design data space

A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.

Method and apparatus for inspecting integrated circuit pattern

Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure's line width to maximize throughput at optimal signal to noise sensitivity. A computer readable medium having programming instructions for performing the above described methods is also disclosed.

Multi-pixel methods and apparatus for analysis of defect information from test structures on semiconductor devices

Disclosed are methods and apparatus for efficiently managing IC chip yield learning. In general terms, as each wafer lot moves through fabrication, yield information is obtained from each set of test structures for a particular process or defect mechanism. The nature of the yield information is such that it may be used directly or indirectly to predict product wafer test yield. In one implementation, the yield information includes a systematic yield (Y 0 ), a defect density (DD), and a defect clustering factor (α) determined based on the inspected test structure's yield. A running average of the yield information for each process or defect mechanism is maintained as each wafer lot is processed. As a particular wafer lot moves through the various processes, a product wafer-sort test yield may be predicted at any stage in the fabrication process based on the running-average yield information maintained for previously fabricated wafer lots.

Methods and systems for predicting IC chip yield

Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Test structures and methods for inspection of semiconductor integrated circuits

Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Multiple directional scans of test structures on semiconductor integrated circuits

Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

Akella V. S. Satya

Papers

Multi-pixel methods and apparatus for analysis of defect information from test structures on semiconductor devices

Methods and systems for predicting IC chip yield

Test structures and methods for inspection of semiconductor integrated circuits

Multiple directional scans of test structures on semiconductor integrated circuits

Inspectable buried test structures and methods for inspecting the same