CuO grown by room-temperature direct current reactive magnetron sputtering is introduced to realize p-type thin-film transistors (TFTs) with a high-k HfO 2 gate dielectric fabricated by atomic layer deposition. The devices work in an accumulation mode (AM) with two apparent threshold voltages corresponding to the formation of a buried channel and an accumulation layer, respectively. A CuO AM TFT with a channel length of 25 μm exhibit a competitive on-off ratio ( I on /I off ) of 1.3 × 10 2 , a subthreshold swing ( SS) of 1.04 V dec −1 , and a field-effect mobility ( μ FE ) of 1.1 × 10 −3 cm 2 V −1 s −1 at room temperature. By measuring a CuO metal oxide semiconductor (MOS) capacitor at room temperature, a high acceptor doping density ( N A ) of ∼5 × 10 17 cm −3 , a high positive effective fixed surface charge density ( Q f ) of ∼9 × 10 12 cm −2 , and a low interfacial trap charge density ( D it ) of ∼6 × 10 10 eV −1 cm −2 at the HfO 2 /CuO interface are estimated. The μ FE extracted from the accumulation regime appears lower than the Hall mobility measured for a similarly processed CuO layer on glass due to the increased hole concentration in CuO TFTs, compared to a Hall concentration of ∼10 14 cm −3 , following the MOS process. SS appears limited by the decreased channel to gate capacitance ( C cg ) related to the buried channel in AM TFTs, parasitic capacitance to ground, and potentially very high interfacial traps at the non-passivated CuO/air interface. 

Room-temperature DC-sputtered p-type CuO accumulation-mode thin-film transistors gated by HfO<sub>2</sub>

In this work, the effects of the atomic-layer deposition (ALD)-derived Al2O3 passivation layer with different growth cycles on the interfacial chemistry and electrical performance of sputtering-driven ErSmO/InP metal oxide semiconductor (MOS) capacitors have been comparatively investigated. Atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS) characterization have confirmed that the ALD-driven Al2O3 passivation layer with 20 growth cycles could form a flat dielectric layer and effectively suppress the diffusion of In and P elements at the InP interface. Meanwhile, the ErSmO/Al2O3/InP gate stack with 20 growth cycles exhibited optimal electrical properties, including a large dielectric constant of 37.42, a minimum interface state density (Dit) of 5.43 × 1011 eV–1 cm–2, and a low leakage current of 3.95 × 10–6 A/cm–2. The leakage current conduction mechanisms of InP-MOS capacitors measured at room temperature and low temperature have also been systematically analyzed. Particularly, low-frequency noise (LFN) is used to evaluate trap levels in InP-MOS capacitors. All experimental results have demonstrated that the ErSmO/Al2O3/InP gate stack has potential applications in future ultrahigh-speed and high-frequency microelectronic devices. 

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al2O3 Interlayers

In this work, p-substrate MOS capacitors with plasma-enhanced atomic-layer-deposited Al2O3/ thermally-grown SiO2 dielectric stack (with a target equivalent oxide thickness of 4.2 nm) are investigated by means of the conductance method in a temperature range from 25°C to 150°C. The trap state density and energy level distribution in the silicon bandgap are extracted over the bandgap. Furthermore, negative bias temperature instability is analyzed by two-point capacitance-voltage characterization to evaluate the electrical stability and dielectric reliability of the Al2O3/SiO2 stack. The contributions from interface and oxide trap generations are detailed. Our results indicate that plasma-enhanced atomic layer deposited Al2O3 on thermal SiO2 stack features low interface trap density, and comparable dielectric reliability to conventional SiO2, SiOxNy, and high-k dielectric stacks. 

Analysis of Trap Distribution and NBTI Degradation in Al2O3/SiO2 Dielectric Stack

Structural and optical properties of Fe@C doped TiO2 thin films prepared by sol-gel method

A high-quality ultrathin dielectric film is important in the field of microelectronics. We designed a composite structure composed of Al2O3/HfO2 with different Al2O3/HfO2 cycles prepared by atomic layer deposition (ALD) to obtain high-quality ultrathin (1-12 nm) dielectric films. Al2O3 protected HfO2 from interacting with the Si substrate and inhibited the crystallization of the HfO2 film. High permittivity material of HfO2 was adopted to guarantee the good insulating property of the composite film. We investigated the physical properties as well as the growth mode of the composite film and found that the film exhibited a layer growth mode. The water contact angle and grazing-incidence small-angle X-ray scattering analyses revealed that the film was formed physically at 3 nm, while the thickness of the electrically stable film was 10 nm from grazing-incidence wide-angle X-ray scattering and dielectric constant analyses. The composite film was applied as a dielectric layer in thin-film transistors (TFTs). The threshold voltage was decreased to 0.27 V compared to the organic field-effect transistor with the single HfO2 dielectric, and the subthreshold swing was as small as 0.05 V/dec with a carrier mobility of 49.2 cm2/V s. The off-current was as low as 10-11 A, and the on/off ratio was as high as 5.5 × 106. This ALD-prepared composite strategy provides a simple and practical way to obtain the high-quality dielectric film, which shows the potential application in the field of microelectronics.

Akihisa Shioi

Papers

Characterization of thin Al2O3/SiO2 dielectric stack for CMOS transistors