Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Semiconductor devices and methods of manufacture thereof

A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric V t for the PMOS and NMOS FETs.

CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof

A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.

Semiconductor device and fabricating method thereof

Methods of forming CMOS devices and structures thereof. A workpiece is provided having a first region and a second region. A high k gate dielectric material is formed over the workpiece. A first gate material comprising a first metal is formed over the high k gate dielectric material. The first gate material in the second region is implanted with a material different than the first metal to form a second gate material comprising a second metal. The work function of the CMOS device is set by the material selection of the gate materials.

Transistor device and method of manufacture thereof

A semiconductor integrated circuit device of the invention includes: a first power supply system including a first circuit connected with a first power supply line; a second power supply system including a second circuit connected with a second power supply line; a signal line connected between the first circuit and the second circuit, and transmitting a signal between the first circuit and the second circuit; a discharge path which is different from the signal line and through which an abnormal current flows when an abnormal voltage is applied between the first power supply system and the second power supply system; a detecting circuit for detecting a potential difference between two positions in the discharge path through which the abnormal current flows when the abnormal voltage is generated; and a protective circuit that operates based on an output of the detecting circuit to suppress a voltage increase of the signal line.

Semiconductor integrated circuit device

A semiconductor device is provided and contains a semiconductor substrate, a first transistor, and a second transistor. The first transistor is formed on the semiconductor substrate and has a first gate electrode. The second transistor is formed on the semiconductor substrate and has a second gate electrode. Also, the thickness of the first gate electrode is different than the thickness of the second gate electrode. Also, a method for forming the semiconductor device is provided.

Semiconductor device and semiconductor device manufacturing method

A semiconductor device has electrostatic protection device capable of preventing characteristic fluctuation of MOS transistor caused by electrostatic discharge. PN junction is formed in between N+ cathode region and boron upward diffusion region of P+ substrate, thus being formed low breakdown voltage diode whose breakdown occurs at low reverse voltage. The diode is in use as electrostatic protection device of either input circuit or output circuit so that it is capable of protecting internal device transistor efficiently from applied surge when gate oxide film becomes thin film.

Semi-conductor device protected by electrostatic protection device from electrostatic discharge damage

In a semiconductor device having MOS transistors, protective elements are connected to gate electrodes 5 - b and 5 - c each of which is an independent gate electrode through the first aluminum layers 7 - a and 7 - d . The first aluminum layers 7 - a and 7 - d are the wiring layers of the lowest layer. The protective elements are constituted by a junction of N well 1 and P + diffused layer 3 - f and a junction of P well 2 and N + diffused layer 4 - f , and a junction of N well 1 and P + diffused layer 3 - g and a junction of P well 2 and N + diffused layer 4 - g.

Semiconductor device capable of preventing gate oxide film from damage by plasma process and method of manufacturing the same

An integrated circuit device capable of testing manufacturing errors such as variations in dimensions at a masking step or the like or misalignment at an alignment step in a plurality of directions with a test circuit having a monitor transistor. The integrated circuit device has a functional circuit for performing a function assigned to the integrated circuit device and a test circuit. The test circuit comprises a plurality of MIS (Metal-Insulator-Semiconductor) transistors each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another. Typically, the integrated circuit device has a rectangular shape in which the test circuit is disposed inside of each vertex thereof. The test circuit is typically formed from four MOS (Metal-Oxide-Semiconductor) transistors having gate electrodes projecting in directions different from one another by approximately 90 degrees.

Integrated circuit device and semiconductor wafer having test circuit therein

An electrostatic protection device for use in a semiconductor integrated circuit, includes a base region of a first conductivity type formed at a principal surface of a semiconductor substrate, a plurality of collector regions constituted of a plurality of first diffused regions of a second conductivity type opposite to the first conductivity type. The first diffused regions are formed on a surface of the base region in the form of a plurality of strips parallel to each other but separate from each other. Emitter regions are constituted of a second diffused region of the second conductivity type formed in the form of a strip between each pair of adjacent collector regions of the plurality of collector regions and a third diffused region of the second conductivity type formed under a contact hole formed in at least one portion of a boundary region at a side of the second diffused region adjacent to the collector region, the third diffused region being connected to the second diffused region. A base contact region of the first conductivity having a high impurity concentration is formed within the base region so as to substantially surround the collector regions and the emitter regions.

Akira Shida

Papers

Semiconductor device and semiconductor device manufacturing method

Semi-conductor device protected by electrostatic protection device from electrostatic discharge damage

Semiconductor device capable of preventing gate oxide film from damage by plasma process and method of manufacturing the same

Integrated circuit device and semiconductor wafer having test circuit therein

Electrostatic protection device for use in semiconductor integrated circuit