Patent
Semi-conductor device protected by electrostatic protection device from electrostatic discharge damage
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TLDR
In this article, the PN junction is formed in between N+ cathode region and boron upward diffusion region of P+ substrate, thus being formed low breakdown voltage diode whose breakdown occurs at low reverse voltage.Abstract:
A semiconductor device has electrostatic protection device capable of preventing characteristic fluctuation of MOS transistor caused by electrostatic discharge. PN junction is formed in between N+ cathode region and boron upward diffusion region of P+ substrate, thus being formed low breakdown voltage diode whose breakdown occurs at low reverse voltage. The diode is in use as electrostatic protection device of either input circuit or output circuit so that it is capable of protecting internal device transistor efficiently from applied surge when gate oxide film becomes thin film.read more
Citations
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Electrostatic discharge protection circuit
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TL;DR: In this paper, an electrostatic discharge protection circuit coupled between an I/O pad and an internal circuit of an IC is described, and the breakdown voltage of the third diode is substantially smaller than the breakdown voltages of the first diode or the second diode.
References
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Patent
Integrated circuit device having vertical MOS provided with Zener diode
TL;DR: In this article, a vertical MOS is made in a single semiconductor substrate having a highly doped underlying layer and a lightly doped epitaxial surface layer of a first conductivity type.
Patent
Integrated circuits having improved electrostatic discharge capability
TL;DR: In this paper, the gate electrodes of MOS transistors are coupled to the well region so that at the onset of reverse P-N junction breakdown between one or more of the drain regions (e.g., N-type), the potentials of the gate electrode of the MOS transistor cells are increased, which causes the breakdown voltages of other nonconducting drain regions to be lowered to initiate breakdown.
Proceedings ArticleDOI
Internal ESD transients in input protection circuits
Y. Fong,Chenming Hu +1 more
TL;DR: In this article, the operation of a gate-oxide transistor under electrostatic discharge (ESD) stress was investigated using a special test circuit, and it was determined that no degradation of the first gateoxide transistor took place under ESD stress.
Patent
MOS transistor with an integrated protection zener diode
TL;DR: In this article, a MOS transistor is formed in a first low-doped P-type retion coating a second more highly doped p-type region, and the transistor comprises an N-type drain region, an n-type source region and a region contacting the for region.
Patent
Mis type semiconductor device
TL;DR: In this paper, the authors proposed to prevent a gate oxide film of an active element from being destroyed owing to static electricity by disposing a static electricity breakdown preventing element in a minus conductivity type semiconductor substrate, on which the active element is disposed, or in a well higher in impurity concentration than the same conductivity types or opposite conductivities in the substrate.