Generally speaking, in accordance with the invention, an optical transmission modulation apparatus is provided for modulating light transmitted through the apparatus. The apparatus comprises a metal film having a periodic array of subwavelength-diameter holes provided therein, and a supporting layer. At least a portion of the supporting layer has a selectively variable refractive index, the selectively variable refractive index portion being substantially adjacent to the metal film such that the metal film and the supporting layer form a perforated metal film unit. Selective variation of the refractive index of the selectively variable refractive index portion modulates the intensity of the light transmitted through the perforated metal film unit without substantially changing the direction of the light. Flat panel displays, spatial light modulators and tunable optical filters based on the optical transmission control apparatus are also provided.

Optical transmission control apparatus utilizing metal films perforated with subwavelength-diameter holes

An apparatus for enhanced light transmission is provided. The apparatus comprises a metal film having a first surface and a second surface, at least one aperture provided in the metal film and extending from the first surface to the second surface, and a periodic surface topography provided on at least one of the first and second surface of the metal film. Light incident on one of the surfaces of the metal film interacts with a surface plasmon mode on at least one of the surfaces of the metal film thereby enhancing transmission of light through the at least one aperture in the metal film. The apparatus may have a single aperture or a plurality of periodically arranged apertures. Wavelength-selective optical filters, spatial optical filters, light collectors, near-field scanning optical microscope probes and photolithographic masks are also provided.

Enhanced optical transmission apparatus utilizing metal films having apertures and periodic surface topography

A surface-plasmon enhanced photovoltaic device including: a first metallic electrode having an array of apertures, an illuminated surface and an unilluminated surface, at least one of the surfaces having an enhancement characteristic resulting in a resonant interaction of incident light with surface plasmons; a second electrode spaced from the first metallic electrode; and a plurality of spheres corresponding to the array of apertures and disposed between the first metallic and second electrodes, each sphere having a first portion of either p or n-doped material and a second portion having the other of the p or n-doped material such that a p-n junction is formed at a junction between the first and second portions.

Surface-plasmon enhanced photovoltaic device

An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition. This technique can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication. The extensions to the algorithm to permit replication are easily implemented and maintain the linear-time complexity of the algorithm. This technique is dependent solely upon the interconnect topology and the direction of signal flows between cells and nets. The formulation of cell gains is extended to model the effect of cell replication, and the necessary modifications to the algorithm are described. >

A cell-replicating approach to minicut-based circuit partitioning

An electron beam exposure apparatus, which illuminates a mask with light emitted by a light source, photoelectrically converts the light patterned by the mask using a photoelectric converter, and exposes an object to be exposed with a patterned electron beam emitted by the photoelectric converter The apparatus includes an electron optical system for imaging the electron beam emitted by the photoelectric converter onto the object, an axial shifter for shifting an optical center of the electron optical system in a direction perpendicular to an optical axis, an axial deflector for deflecting the electron beam that propagates in the electron optical system, a region limiter for limiting a region of the mask to be projected onto the object via the photoelectric converter and the electron optical system to a partial region of the mask, and a scan controller for scanning the object with the region-limited electron beam by changing the partial region to be limited while controlling the axial shifter and axial deflector

Electron beam exposure apparatus

This paper presents new algorithms for cell pattern generation. The evaluated cell areas are based on measurements which are independent of production process technology. The placement algorithm recognizes logic gates from an unconstrained CMOS circuit diagram and places them in a pattern which minimizes the total wiring length. The generated cell pattern has bent gates and is grid-free. This generator has been applied to more than 60 cell designs used for industrial chips without the need of manual intervention.

A high packing density module generator for CMOS logic cells

An electron beam lithography apparatus is disclosed which has an aperture plate provided with an aperture including an array of repeated unit patterns and an ordinary aperture of a rectangular shape. A region free of the influence of a proximity effect is delineated using the former aperture, and a region affected by the proximity effect is delineated using the latter aperture. The number of repeated unit patterns included in the former aperture is determined considering the number of repeated unit patterns included in a pattern array to be delineated on a substrate. Thereby, the number of electron beam shots is reduced. A plurality of apertures having slightly different aperture widths may be provided for always keeping a pattern line width constant.

Electron beam lithography using an aperture having an array of repeated unit patterns

A new pattern operation algorithm effective for VLSI mask data is presented. It conducts intersection-point calculation, slit division, and logical processing simultaneously. A new algorithm for intersection-point calculation is also presented. Using these algorithms, a pattern operation program package (VSOP) has been developed that is applicable to several mask artwork systems in common, and that has 21 functions. The execution time for VSOP varies approximately in proportion to the number of input vectors. CPU time for 1,000,000 vectors is 200 seconds.

A Concurrent Pattern Operation Algorithm for VLSI Mask Data

A fast checking algorithm and evaluation of a high-hitting pattern checker (MACH) for VLSI mask data are presented. A two-dimensional-limited searching algorithm has realized O(Nv), where Nv is the number of vectors. The processing speed of MACH is 6,000 vectors per second. MACH can handle VLSI data of more than 10,000,000 vectors that include diagonal vectors. The designer can describe arbitrary design rules using a Design Rule Description Language. We have defined two quality measures for a pattern checker, that is, Detecting Rate and Hitting Rate. MACH has achieved the best detecting rate of 100% and a high hitting rate of more than 80%.

MACH: A High - Hitting Pattern Checker for VLSI Mask Data

With the advance of scale and integrity of LSIs, several kinds of CAD systems are being developed and introduced to design verification and mask pattern generation for mask pattern data as a means of shortening the design time. The processings common to these CAD systems are pattern logical operations. This paper proposes effective and fast pattern operation algorithms for large-scale data containing patterns of any angle: the virtual slit method and limited searching algorithm. The virtual slit method is a logical operation algorithm performing concurrently the three processings, intersection-point calculation, slit division, and logical processing which have been done independently in old algorithms. The limited searching algorithm is a highspeed intersection-point calculation algorithm indispensable for diagonal figures. The time complexity of both methods is theoretically O(Nv) log Nv) where Nv is the number of input vectors. For manufactured LSI mask data, we obtained the result for the time complexity based on estimation by program execution which can be approximated by O(Nv).

Akira Tsukizoe

Papers

A high packing density module generator for CMOS logic cells

Electron beam lithography using an aperture having an array of repeated unit patterns

A Concurrent Pattern Operation Algorithm for VLSI Mask Data

MACH: A High - Hitting Pattern Checker for VLSI Mask Data

A concurrent pattern operation algorithm for VLSI mask data