Showing papers by "Alberto Sangiovanni-Vincentelli published in 1984"

Logic Minimization Algorithms for VLSI Synthesis

Abstract: 1. Introduction.- 1.1 Design Styles for VLSI Systems.- 1.2 Automatic Logic Synthesis.- 1.3 PLA Implementation.- 1.4 History of Logic Minimization.- 1.5 ESPRESSO-II.- 1.6 Organization of the Book.- 2. Basic Definitions.- 2.1 Operations on Logic Functions.- 2.2 Algebraic Representation of a Logic Function.- 2.3 Cubes and Covers.- 3. Decomposition and Unate Functions.- 3.1 Cofactors and the Shannon Expansion.- 3.2 Merging.- 3.3 Unate Functions.- 3.4 The Choice of the Splitting Variable.- 3.5 Unate Complementation.- 3.6 SIMPLIFY.- 4. The ESPRESSO Minimization Loop and Algorithms.- 4.0 Introduction.- 4.1 Complementation.- 4.2 Tautology.- 4.2.1 Vanilla Recursive Tautology.- 4.2.2 Efficiency Results for Tautology.- 4.2.3 Improving the Efficiency of Tautology.- 4.2.4 Tautology for Multiple-Output Functions.- 4.3 Expand.- 4.3.1 The Blocking Matrix.- 4.3.2 The Covering Matrix.- 4.3.3 Multiple-Output Functions.- 4.3.4 Reduction of the Blocking and Covering Matrices.- 4.3.5 The Raising Set and Maximal Feasible Covering Set.- 4.3.6 The Endgame.- 4.3.7 The Primality of c+.- 4.4 Essential Primes.- 4.5 Irredundant Cover.- 4.6 Reduction.- 4.6.1 The Unate Recursive Paradigm for Reduction.- 4.6.2 Establishing the Recursive Paradigm.- 4.6.3 The Unate Case.- 4.7 Lastgasp.- 4.8 Makesparse.- 4.9 Output Splitting.- 5. Multiple-Valued Minimization.- 6. Experimental Results.- 6.1 Analysis of Raw Data for ESPRESSO-IIAPL.- 6.2 Analysis of Algorithms.- 6.3 Optimality of ESPRESSO-II Results.- 7. Comparisons and Conclusions.- 7.1 Qualitative Evaluation of Algorithms of ESPRESSO-II.- 7.2 Comparison with ESPRESSO-IIC.- 7.3 Comparison of ESPRESSO-II with Other Programs.- 7.4 Other Applications of Logic Minimization.- 7.5 Directions for Future Research.- References.

Relaxation-Based Electrical Simulation

Abstract: Circuit simulation programs have proven to be most important computer-aided design tools for the analysis of the electrical performance of integrated circuits. One of the most common analyses performed by circuit simulators and the most expensive in terms of computer time is nonlinear time-domain transient analysis. Conventional circuit simulators were designed initially for the cost-effective analysis of circuits containing a few hundred transistors or less. Because of the need to verify the performance of larger circuits, many users have successfully simulated circuits containing thousands of transistors despite the cost. Recently, a new class of algorithms has been applied to the electrical IC simulation problem. New simulators using these methods provide accurate waveform information with up to two orders of magnitude speed improvement for large circuits. These programs use relaxation methods for the solution of the set of ordinary differential equations, which describe the circuit under analysis, rather than the direct sparse-matrix methods on which standard circuit simulators are based. In this paper, the techniques used in relaxation-based electrical simulation are presented in a rigorous and unified framework, and the numerical properties of the various methods are explored. Both the advantages and the limitations of these techniques for the analysis of large IC's are described

A Computational Approach for the Diagnosability of Dynamical Circuits

Abstract: Based on a discrete-time circuit description, a necessary and sufficient condition is derived for the local diagnosability of the class of dynamical circuits whose branch relations are analytic functions of their arguments. Both the single-fault case and the case where all the parameters are assumed to be faulty are dealt with. The condition is a rank test on a matrix that is determined from a single circuit simulation and sensitivity computation. The technique is illustrated with an example.

Comparisons and Conclusions

Abstract: In this chapter we recapitulate the main features of ESPRESSO-II and compare it to other minimization algorithms. We compare its strategy with that of MINI, POP and PRESTO, and discuss some modifications introduced in the C-language version of ESPRESSO-II. We then present empirical results obtained by running these programs on the 56 test cases introduced in the preceding chapter. Finally, we discuss other applications of logic minimization and directions for further research.

Pleasure: a computer program for simple/multiple constrained/unconstrained folding of programmable logic arrays

Abstract: Programmable logic arrays are important building blocks of VLSI circuits and systems The problem of optimizing the silicon area and the performances of large logic arrays are addressed In particular a general method is described for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry A constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs is defined A new computer program, PLEASURE is presented It implements several algorithms for multiple and/or constrained PLA folding

Multiple-Valued Logic Minimization

Abstract: As discussed in Chapter 1, many multiple-valued input logic functions can be implemented very efficiently in PLA’s with two-bit input decoders. Hence multiple-valued logic minimization is of great practical importance [FLE 75]. A two-bit decoder pairs two Boolean variables, say x1 and x2, and generates four decodes $$ \begin{array}{*{20}{c}} {{{x}_{1}}{{x}_{2}},} \\ {{{{\bar{x}}}_{1}}{{x}_{2}},} \\ {{{x}_{1}}{{{\bar{x}}}_{2}},} \\ {{{{\bar{x}}}_{1}}{{{\bar{x}}}_{2}}.} \\ \end{array} $$

The Espresso-II Minimization Loop and Algorithms

Abstract: ESPRESSO-II receives as its inputs J and D, cube covers of the on-set and the don’t-care set of an incompletely specified Boolean function ff. Optionally, it can accept input J and Rx, cube covers of the on- and off-sets. It returns as its output a “minimized” cover. As discussed in Chapter 1, the objectives of ESPRESSO-II are to minimize: NPT: the number of product terms in the cover; NLI: the number of literals (non-2’s) in the input parts of the cover; NLO: the number of literals in the output parts.