An apparatus and method for clock rate matching in independent networks is disclosed. The apparatus accepts data from a modem (126) into a buffer (400) and determines the difference between the rate of the data entering the buffer (400) at the modem clock rate to the rate of data exiting the buffer (400) at the clock rate used by the apparatus. Depending on the rate difference, the apparatus either speeds up or slows down the data rate accordingly.

Clock rate matching in independent networks

For use in a multi-node digital network wherein the local clocks of all the nodes are required to be maintained in synchronism, and corrections are required to be effected for changes in propagation times of inter-node links. A clock deviation at either of two link-connected nodes is oppositely detected at both nodes, and this results in each node transmitting, in place of a normal "do-nothing" signal, an "advance" or a "retard" signal (i.e. opposite types) to the other to correct for the deviation. Each signal transmitted is allowed to be operative on the clock at the receiving node only if no other link, terminated on that node, is producing a contrary signal. Thus the clock of the node which has drifted is subjected to correction by a signal from the partner node. As regards a change in propagation-delay of the link (same for each direction of transmission) this results in both nodes of the effected link transmitting identical "advance" or "retard" signals to the partner. These signals are assessed at each node as a demand in each case to similarly adjust the timing off-set appertaining to the frame alignment signal.

Synchronization arrangements for digital switching centers

A clocking system is disclosed for a multichannel data transmission system which includes a temporary storage medium, such as magnetic tape. The system is an improvement over prior art systems which utilize a separate phase locked loop clock correction circuit for each channel. The described system utilizes a single clock for the multiple channels which operates at a frequency F that is an integral multiple of the channel baud rate. Means are provided to continually monitor the phase error of each channel and a composite correction signal is derived and applied to the clock signal which is proportional to the average of the phase errors of the individual channels.

Multichannel common clock

A synchronized phase adjustment system provides relative synchronization of the clock oscillators in a mesh-connected parallel processor. Each node of a mesh contains an independent voltage controlled oscillator, and each node is linked to adjacent nodes by phase detectors. The phase differences between a node oscillator and the oscillators of adjacent nodes are combined by an input circuit the output of which is an average value applied to the node oscillator. The transfer function of the signal input to an oscillator relative to detected phase error indicates the restoring force (voltage) which is provided to adjust the phase of that oscillator. It is shown that a stable latch-up state in which all node phases of a mesh are not equal requires that one of the phase differences between two nodes is greater than π/2. Thus, the transfer function of the signal input to an oscillator is given a negative slope for phase differences having an absolute value between Sg(p)/2 and π. For smooth response, the transfer function is given a positive slope for phase differences closer to zero, a particular embodiment having a transfer function with an absolute value between 0 and π/2.

Synchronization of hardware oscillators in a mesh-connected parallel processor

In a sliding bearing, a metallic layer is coated on a bearing base bush and is provided with grooved or helical or crossing indentations with intermediate elevations. Applied in a uniform manner onto the so-formed metallic layer is a sliding layer of softer material. Under pressure or application of shear forces, the material of the sliding layer provided above the elevations is forced through plastic shaping to flow into the indentations so as to provide a levelled and smooth sliding surface covering the metallic layer.

Apparatus for fabricating a plain (sliding) bearing

A method and apparatus are described synchronizing oscillators at the network junctions in a pulse code modulation (PCM), time division multiplex (TDM) telecommunication network. In each network node pulse trains of clock pulses are received via incoming lines, and corresponding clock pulse trains are produced in the network node in accordance with the node's clock frequency division factor. The received and locally produced pulse trains are phase-compared, and a control signal resulting from the comparison is used to control the frequency of the clock oscillator in the network node. In each network node of a first network which has a direct line connection to a network node in a second network a phase comparison takes place between the two networks, and the result of the latter comparison is compared with the result of an intra-network comparison. The result of the latter comparison is used to adjust the line clock frequency of a given network.

Method and switching arrangement for synchronizing oscillators of a digital telecommunication network

Verfahren und schaltungsanordnung zur synchronisierung von oszillatoren eines digital-fernmeldenetzes durch oszillatoren eines weiteren fernmeldenetzes

Alexander Dipl Ing Dragotinov

Papers

Method and switching arrangement for synchronizing oscillators of a digital telecommunication network

Verfahren und schaltungsanordnung zur synchronisierung von oszillatoren eines digital-fernmeldenetzes durch oszillatoren eines weiteren fernmeldenetzes