A
Ali A Poursepanj
Researcher at IBM
Publications - 5
Citations - 120
Ali A Poursepanj is an academic researcher from IBM. The author has contributed to research in topics: Execution unit & Addressing mode. The author has an hindex of 4, co-authored 5 publications receiving 120 citations.
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Patent
Method and System for Single Cycle Dispatch of Multiple Instructions in a Superscalar Processor System
A Curley James,Chin-Cheng Kau,David S Levitan,Aubrey D Ogden,Ali A Poursepanj,Paul Kang-Guo Tu,Donald E Waldecker +6 more
TL;DR: In this article, a method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers is presented.
Journal ArticleDOI
The PowerPC performance modeling methodology
TL;DR: The PowerPC performance modeling was based on trace-driven simulation, where the microprocessor organization is specified as a model, benchmark traces are generated and applied to the model, and performance data is measured and analyzed.
Patent
Method and system for selective serialization of instruction processing in a superscalar processor system
James Allan Kahle,Chin-Cheng Kau,Aubrey D Ogden,Ali A Poursepanj,Paul Kang-Guo Tu,Donald E Waldecker +5 more
TL;DR: In this paper, the authors present a method and system that permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the instructions to a plurality of execution units on a nonsequential opportunistic basis.
Patent
Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage
James Allan Kahle,Chin-Cheng Kau,Aubrey D Ogden,Ali A Poursepanj,Paul Kang-Guo Tu,Donald E Waldecker +5 more
TL;DR: In this paper, a method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers is presented.