In the quest for ever-reducing system size and increased integration and functionality, application-specific integrated circuit (ASIC) technology plays a pivotal role in modern implants, where custom circuits designed at transistor and device levels are replacing off-the-shelf commercial chips and bulky benchtop systems. Recently, commercial system-on-chip (SoC) devices encompassing digital microcontrollers, radio, and analog–digital converters, as well as reconfigurable amplifier circuits, are widely available. Despite this, further development of ASIC-specific implantable systems is required, particularly in the area of multi-channel array sensor interfaces, ultra-low power data acquisition, and circuits that work with specialized micro-sensors for implants. ASICs designed to focus on a particular application have given designers the freedom to optimize power consumption for a set task, unlike general-purpose SoCs that have to cater for a wide range of applications and hence typically consume more power. In this chapter, we begin with a survey on the latest development of ASICs and related integrated systems from literature. This is followed by an overview of technological trends in integrated circuit/sensor fabrication and fusion. The rest of the chapter focuses on a number of engineering aspects related to ultra-low power ASIC circuits appropriate for implantable sensors and sensor front-ends, covering bioimpedance, neural and electrochemical sensor measurement circuits, as well as low-power analog-to-digital converter design and architectures.

Ultra-Low Power Application-Specific Integrated Circuits for Sensing

It is well known that fully differential (FD) structures have many advantages over their single-ended counterparts. However, the main disadvantage of FD circuit is the potential instability caused by the inherent common-mode (CM) positive feedback loop. To solve such an instability problem, extra common-mode feedback (CMFB) and/or common-mode feedforward (CMFF) circuitries are often incorporated to stabilise the circuits. We present a systematic method for checking the stability condition and identifying the most suitable CMFB network connection for a particular FD Gm-C filter. It has been demonstrated that the CMFB network connection that provides highest CM rejection is not necessarily the conventional arrangement commonly used in FD Gm-C design.

Selection of the common-mode feedback network connection of fully differential Gm-C filters

This paper presents a new topology for realizing current-mode reconfigurable nth-order filter for multi-mode wireless communication equipments, which is based on a new active device, namely digitally programmable current differencing transconductance amplifier (DPCDTA). The proposed filter is resistorless, and it employs n DPCDTAs and n grounded capacitors with one input and one output terminals. The signal path of the filter does not contain any switches, and wide tuning coefficient of the filter is implemented using programmable current division network with zero standby power consumption in the DPCDTA. Also, the proposed topology exhibits broader programmable features to accommodate wide range of selectivity requirements, which can be used as the most compatible structure for field-programmable analog array and very suitable for multi-mode filtering applications. The programming ability of variable filter orders from first to fourth providing low-pass, high-pass, and band-pass responses, and programming ability of variable cutoff frequencies from 1.14 to 11.75 MHz are given as application examples. The performance of the circuits have been verified and evaluated through post-layout simulations using Cadence IC5141 with GlobalFoundries’
 0.18 μm CMOS process.

Resistorless Reconfigurable nth-Order Filter Based on DPCDTA for Multi-mode Filtering Applications

A current-mode field programmable analog array(FPAA) is presented in this paper. The proposed FPAA consists of 9 configurable analog blocks(CABs) which are based on current differencing transconductance amplifiers (CDTA) and trans-impedance amplifier (TIA). The proposed CABs interconnect through global lines. These global lines contain some bridge switches, which used to reduce the parasitic capacitance effectively. High-order current-mode low-pass and band-pass filter with transmission zeros based on the simulation of general passive RLC ladder prototypes is proposed and mapped into the FPAA structure in order to demonstrate the versatility of the FPAA. These filters exhibit good performance on bandwidth. Filter’s cutoff frequency can be tuned from 1.2MHz to 40MHz.The proposed FPAA is simulated in a standard Charted 0.18μm CMOS process with ±1.2V power supply to confirm the presented theory, and the results have good agreement with the theoretical analysis.

Field programmable analog array based on current differencing transconductance amplifiers and its application to high-order filter

We propose in this paper a programmable band-pass filter based on an array of fully differential transconductance circuits that controls the filter parameters. The signal path does not contain any switch, and fine-tuning of the filter parameters is implemented using programmable capacitors. A digital building block is implemented in the proposed band-pass filter to tune its central frequency as well as its bandwidth. The filter circuit is based on a biquad topology, which is designed and implemented with CMOS 0.18 μm technology. Experimental results show a programming ability of the center frequency between 5.9 and 58 MHz, and the quality factor can be tuned from 0.36 to 10. These features are obtained for a total power consumption of less than 10.5 mW from a single 1.8 V power supply.

Ali Assi

Papers

Programmable monolithic Gm-C band-pass filter: design and experimental results