A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing a fractional- synthesizer as the FMCW generator, the transmitter linearly modulates the carrier frequency across a range of 700 MHz. The receiver together with an external baseband processor detects the distance and relative speed by conducting an FFT-based algorithm. Millimeter-wave PA and LNA are incorporated on chip, providing sufficient gain, bandwidth, and sensitivity. Fabricated in 65-nm CMOS technology, this prototype provides a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2-V supply.

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology

This work proposes a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, and analyzes its performance with Volterra series. The linearization technique is applied to an ultra-wideband (UWB) cascode common gate Low Noise Amplifier (CG-LNA), and two additional reference designs are implemented to evaluate the linearization technique - a standard (without linearization) cascode CG-LNA and a single-transistor CG-LNA. The single-transistor CG-LNA achieves +6.5 to +9.5 dBm IIP3, 10 dB (max.) gain, and 2.9 dB (min.) NF over a 3-11 GHz bandwidth (BW); the LNA consumes 2.4 mW from a 1.3 V supply. The cascode linearized LNA achieves +11.7 to +14.1 dBm IIP3, 11.6 dB (max.) gain, and 3.6 dB (min.) NF over 1.5 to 8.1 GHz; the cascode LNA consumes 2.62 mW from a 1.3 V supply. Experimental results show that the linearization technique improves the cascode LNA's IIP3 by a factor of 3.5 to 9 dB over a 2.5-10 GHz frequency range.

A Low-Power, Linearized, Ultra-Wideband LNA Design Technique

A 15.1 dB gain, 2.1 dB (min.) noise figure low-noise amplifier (LNA) fabricated in 0.13 mum CMOS operates across the entire 3.1-10.6 GHz ultrawideband (UWB). Noise figure variation over the band is limited to 0.43 dB. Reactive (transformer) feedback reduces the noise figure, stabilizes the gain, and sets the terminal impedances over the desired bandwidth. It also provides a means of separating ESD protection circuitry from the RF input path. Bias current-reuse limits power consumption of the 0.87mm2 IC to 9 mW from a 1.2 V supply. Comparable measured results are presented from both packaged and wafer probed test samples

A 1.2 V Reactive-Feedback 3.1–10.6 GHz Low-Noise Amplifier in 0.13 $\mu{\hbox {m}}$ CMOS

A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm2

http://web.nchu.edu.tw/~ycchiang/RFIC/CMOS79764430.pdf

An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18- $\mu$ m CMOS

Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network

This paper presents a 1.5GHz CMOS differential VCO whose close-in phase noise is 20dB lower than in a conventional differ- ential oscillator across the full tuning range. At 50kHz offset, the oscillator's phase noise of -105dBc/Hz is low enough for the PDC receiver. A prototype oscillator (Fig. 5.7.3) is fabricated in the Jazz Semiconductor BC35M process using 0.35µm FETs. The circuit oscillates nominally at 1.5GHz, and its frequency can be tuned from 1.43 to 1.64GHz with an NMOS varactor (20 x 10/0.35µm) in parallel with a 4-bit binary switched capacitor array (80fF unit capacitance). The tank inductor is fabricated as a differen- tial spiral in 3µm thick Metal 3; over the 8 ohm-cm substrate, inductor Q is 9 at 1.5GHz. The tail resistors are realized in unsilicided polysilicon, and the control switch FETs are laid out in a ring gate geometry to lower drain junction capacitance. The oscillator operates from 2.7V and biases at 6mA. Packaged chips are measured on a calibrated RDL NTS-1000A Phase Noise Analyzer. Figure 5.7.4 plots the measured phase noise for a typical chip at the nominal oscillation frequency of 1.5GHz. It is compared with the measured phase noise in an identical chip whose Cc is short- ed, that is, where M1 and M2 merge into the standard differen- tial pair. This serves as a reference oscillator to normalize depen- dencies on fabrication process. Both oscillators are biased at the same current. The flicker noise corner in the new oscillator lies at about 8kHz offset, whereas in the reference oscillator it lies at about 1MHz. In the flicker noise-dominated region, the new oscillator's phase noise is lower by 20dB. At 50kHz offset, phase noise is lower by 15dB. As the varactor control voltage is swept from VDD to ground, the phase noise remains almost constant (Fig. 5.7.5). Across the entire discrete tuning range, the close-in phase noise changes by only about 2dB (Fig. 5.7.6). The degree of suppression is limited by Ctail, which in this prototype is deter- mined by interconnects. The wideband suppression technique presented in this paper is expected to enable use of FET VCOs in applications where previ- ously they were excluded by excessive upconversion of 1/f noise.

Aly Ismail

Papers

A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network

Up-Converted Flicker Noise