This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V DD and V T to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V DD for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-μm test chip is used to compare normal sizing and sizing to minimize operational V DD and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.

Modeling and sizing for minimum energy operation in subthreshold circuits

This paper presents the extended Kalman filter (EKF) and moving horizon estimation (MHE) approach-based nonlinear stochastic filtering of fractional-order complementary metal oxide semiconductor (CMOS) circuit. The fractional-order calculus is used to get better reliability of the circuit. The two metal oxide semiconductor field-effect transistors of CMOS circuit are modeled using Enz–Krummenacher–Vittoz (EKV) model, and Kirchhoff’s current law (KCL) is then applied to obtain the state-space model. Ornstein–Uhlenbeck (O.U.) process is used to model the input source, which is a white Gaussian noise and Brownian process. Following are the advantages of the proposed method: (1) State estimation using EKF and MHE is real-time and can be used for the estimation purpose when parameters are slowly varying with time. (2) Fractional-order calculus leads to better flexibility in circuits. (3) Application of Kronecker product gives better and more accurate nonlinear mathematical representation. The estimated output values obtained using the proposed techniques have been compared with the wavelet transform (WT) method when nonlinear dynamics are represented using Kronecker product-based representation. The estimated output voltage using estimation algorithms is then compared with PSPICE simulated values. Simulation results validate the better disturbance rejection ability of the proposed methods.

Stochastic filtering in fractional-order circuits

We present and discuss explicit closed-form expressions for the saturation drain current of short-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz–Krummenacher–Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert ${W}$ function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-current ratio, can be readily expressed as explicit functions of the terminal voltages.

On the Explicit Saturation Drain Current in the Generalized EKV Compact MOSFET Model

We present an easy but effective method to extract the four parameters of the simplified Enz–Krummenacher–Vittoz (sEKV) MOSFET model. The procedure, which is based on direct lateral optimization, is tested using measurements from experimental polycrystalline silicon Thin Film Transistors (TFTs) of various channel lengths and widths. We demonstrate that this basic MOSFET model is able to reasonably describe the saturation transfer characteristics of these polysilicon TFTs. Furthermore, we evaluate the computational adeptness for extracting the four sEKV parameters of the lateral optimization fitting procedure as compared to the more traditional vertical optimization one. 

Simplified EKV model parameter extraction in polysilicon MOSFETs

Negative bias temperature instability, abbreviated as NBTI, has emerged as the primary reliability challenge for nanoscale PMOS transistors. In this paper, a complete and comprehensive analysis of 22nm PMOS transistor has been carried out for the purpose of determining the degradation of NBTI across both static and dynamic operations. The Support Vector Regression Machine Learning Model has been trained and tested across a set of a thousand data points, with eighty percent of the data serving as training and twenty percent serving as testing. A dataset has been gathered over the course of ten years, and the best-fit machine learning model earned the highest score of 0.99 by utilising Radial Basis (RBF) Function. In comparison, linear and polynomial-based modelling approaches achieved scores of 0.87 and 0.78, respectively. 

Amalendu Bhushan Bhattacharyya

Papers

A Unified Analytical Transregional MOSFET Model for nanoscale CMOS digital technologies