A subthreshold analytical model for Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) is developed. To analyze the behavior of short channel device, relevant parameters such as surface potential, electric field, threshold voltage, drain current, transconductance-to-drain current ratio, subthreshold slope and subthreshold swing are extracted from the 2-D analytical solution of Poisson's equation. Relating DMDG JLTFET to Junctionless MOSFETs, the results show significant reduction of Short Channel Effects (SCEs) at the drain end. The analytical model for DMDG JLTFET is effective due to the combined supremacy of uniform doping in the channel, usage of high-K gate dielectric material and work function engineering in the gate metal. The results obtained from the analytical model are simulated and validated using 2-D Sentaurus TCAD device simulator.

New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation

This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V DD and V T to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V DD for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-μm test chip is used to compare normal sizing and sizing to minimize operational V DD and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.

Modeling and sizing for minimum energy operation in subthreshold circuits

Cryptocircuits can be attacked by third parties using differential power analysis (DPA), which uses power consumption dependence on data being processed to reveal critical information. To protect security devices against this issue, differential logic styles with (almost) constant power dissipation are widely used. However, to use such circuits effectively for secure applications it is necessary to eliminate any energy-secure flaw in security in the shape of memory effects that could leak information. This paper proposes a design methodology to improve pull-down logic configuration for secure differential gates by redistributing the charge stored in internal nodes and thus, removing memory effects that represent a significant threat to security. To evaluate the methodology, it was applied to the design of AND/NAND and XOR/XNOR gates in a 90 nm technology, adopting the sense amplifier based logic (SABL) style for the pull-up network. The proposed solutions leak less information than typical SABL gates, increasing security by at least two orders of magnitude and with negligible performance degradation. A simulation-based DPA attack on the Sbox9 cryptographic module used in the Kasumi algorithm, implemented with complementary metal–oxide–semiconductor, SABL and proposed gates, was performed. The results obtained illustrate that the number of measurements needed to disclose the key increased by much more than one order of magnitude when using our proposal. This paper also discusses how the effectivenness of DPA attacks is influenced by operating temperature and details how to insure energy-secure operations in the new proposals.

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits

In this work, a dual metal (DM) double-gate (DG) Tunnel Field Effect Transistor (DMDG-TFET) with drain-gate underlap is proposed to overcome the challenges in conventional TFET. The ON-current (Ion), OFF-current (Ioff), Ion/Ioff ratio, subthreshold swing (SS) and ambipolar current (Iambi) of the proposed device with drain underlap are investigated as gate length is scaled (LGATE) down. The proposed device gives a better suppression in leakage current and low ambipolar current. The suppressed leakage current (Ioff) and ambipolar current (Iambi) are 9.49 × 10−14 A/µm and 1.95 × 10−12 A/µm respectively for a gate length (LGATE) of 36 nm and a channel length (LCh) of 50 nm for a supply voltage of 0.5 V. Excellent switching behavior is achieved when gate length (LGATE) is 72% of the channel length (LCh). The proposed architecture is suitable for low power applications.

Impact of leakage current in germanium channel based DMDG TFET using drain-gate underlap technique

An improved subthreshold analytical model of Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) with stacked / hetero-dielectric gate oxide structure is proposed. The stacked gate oxide structure comprises of Silicon-dioxide (SiO2) and Titanium Oxide (TiO2). The high-K gate stack engineered device overcomes the Short Channel Effects (SCEs) caused by the ultrathin silicon devices. The subthreshold analysis is carried out by solving a two-dimensional Poisson’s equation using Parabolic approximation method. These characteristics are analyzed against various device parameters. Also, the impact of different high-K gate oxide materials with SiO2 is also studied. A comparative analysis of short channel effects for DMDG TFET and DMDG JLTFET has been carried out. The results reveal that the proposed device provides better ION current, low leakage current and improved Transconductance-to-drain current ratio. Using TCAD Sentaurus device simulator, the subthreshold analytical model results have been simulated and verified with other TFET models.

Improvement of Subthreshold Characteristics of Dopingless Tunnel FET Using Hetero Gate Dielectric Material: Analytical Modeling and Simulation

Analytical circuit design, optimization, characterization and development of design methodology for digital circuits using nanoscale CMOS devices require compact equations. Such equations need to include first order short channel phenomena relevant to the nanoscale technology nodes being used. The present paper demonstrates that α -power model can be updated to include velocity overshoot necessary to characterize devices at ultradeep submicron technology nodes. Further, the three α -power model parameters (velocity saturation index α , transconductance parameter K1 and threshold voltage V th ) expressing MOSFET drain current has been expressed in terms of predictive technology model (PTM) parameters. Representative basic CMOS cells belonging both to inverter and transmission gate categories have been analytically characterized using the updated α -power model up to ultradeep submicron technology node with BSIM verification. It has been shown that consideration of velocity overshoot is important for accurate prediction below 40 nm.

Scalable α-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design

Aggressive technology scaling and an increasing demand of high performance VLSI circuits has resulted in higher current densities and increased power dissipation. A significant fraction of this power is converted to heat and an exponential rise in heat density is experienced. As a consequence, temperature measurement and control are critical tasks in many applications. Temperature variations often alter threshold voltage, carrier mobility and saturation velocity of MOSFET and thereby altering the performance of the CMOS circuits. This paper identifies the device parameters that characterize the variation of MOSFET current due to temperature fluctuations on 180nm CMOS technology. Further, the effect of temperature variation on performance of CMOS digital circuits and optimization of device parameters for temperature variation insensitive performance of the circuit is also presented.

Effect of temperature dependence on performance of Digital CMOS circuit technologies

A Unified Analytical Transregional MOSFET Model for nanoscale CMOS digital technologies

Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model.

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Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold

System security has always been associated with the software being used on it. The hardware has been by default considered trusted. This root of trust for hardware has been violated after the emergence of Hardware Trojan (HT) attacks. Such attacks can be used by an adversary to leak important or secret information or to conduct a system failure. This paper gives a broad overview on different techniques that can be used to detect HT inside a circuit in place of destructive reverse engineering. Further a detailed literature survey has been presented which gives an overview of the efficiency of the detection techniques used in the literature.

Shruti Kalra

Papers

Scalable α-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design

Effect of temperature dependence on performance of Digital CMOS circuit technologies

A Unified Analytical Transregional MOSFET Model for nanoscale CMOS digital technologies

Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold

A Survey on Hardware Trojan Detection: Alternatives to Destructive Reverse Engineering