In this paper we present a design-for-debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.

A reconfigurable design-for-debug infrastructure for SoCs

In this paper, we present a new method for detecting groups of symmetric variables of completely specified Boolean functions. The canonical Generalized Reed-Muller (GRM) forms are used as a powerful analysis tool. To reduce the search space we have developed a set of signatures that allow us to identify quickly sets of potentially symmetric variables. Our approach allows for detecting symmetries of any number of inputs simultaneously. Totally symmetric functions can be detected very quickly. The traditional definitions of symmetry have also been extended to include more types. This extension has the advantage of grouping input variables into more classes. Experiments have been performed on MCNC benchmark cases and the results verify the efficiency of our method.

Generalized Reed-Muller forms as a tool to detect symmetries

A new mathematically based method of synthesis for combinational digital networks is presented, based upon the recognition of symmetry patterns in the functions being synthesized. The design procedure is structured such that at each stage of the synthesis a relevant gate assembly is indicated, which leaves a simplified "remainder" function to be synthesized at the next stage of the realization. This decomposition procedure optimally uses gates with a fan in of two, but post-synthesis reconfiguration for amalgamation into larger fan-in gates is available.

A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods

In this paper we present a new method for Boolean matching of completely specified Boolean functions. The canonical Generalized Reed-Muller forms are used as a powerful analysis tool. Input permutation, as well as input and output negation for matching are handled simultaneously. To reduce the search space for input correspondence, we have developed a method that can detect symmetries of any number of inputs simultaneously. Experiments on MCNC benchmark circuits are very encouraging.

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Boolean Matching Using Generalized Reed-Muller Forms

Symmetry detection in completely specified Boolean functions is important for several applications in logic synthesis, technology mapping, binary decision diagram (BDD) minimization, and testing. This paper presents a new algorithm to detect four basic types of two-variable symmetries. The algorithm detects all pairs of symmetric variables in one pass over the shared BDD of the multioutput function. The worst case complexity of this method is cubic in the number of BDD nodes, but on typical logic synthesis benchmarks the complexity appears to be linear. The computation is particularly efficient when the functions have multiple symmetries or no symmetries. Experiments show that the algorithm is faster than other known methods, and in some cases achieves a speedup of several orders of magnitude.

Amarendra Mukhopadhyay

Papers

Detection of Total or Partial Symmetry of a Switching Function with the Use of Decomposition Charts