Amir H. Ajami

TL;DR: This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.

TL;DR: It is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations.

TL;DR: In this article, a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies is presented, where the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis.

TL;DR: A non-uniform temperature-dependent distributed RC interconnect delay model is proposed for the first time and has been applied to a wide variety of interconnect layouts and temperature distributions to quantify the impact on signal integrity issues including clock skew fluctuations.

TL;DR: Using a novel non-uniform temperature-dependent distributed RC interconnect delay model, the behavior of clock skew in the presence of the substrate thermal gradients is analyzed and some design guidelines are provided to ensure the integrity of the clock signal.