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Amirali Shayan
Researcher at University of California, San Diego
Publications - 19
Citations - 287
Amirali Shayan is an academic researcher from University of California, San Diego. The author has contributed to research in topics: Switched-mode power supply & Voltage regulator. The author has an hindex of 10, co-authored 19 publications receiving 282 citations. Previous affiliations of Amirali Shayan include Qualcomm.
Papers
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Proceedings ArticleDOI
Dynamically heterogeneous cores through 3D resource pooling
TL;DR: This paper describes an architecture for a dynamically heterogeneous processor architecture leveraging 3D stacking technology that enables runtime customization of cores at a fine granularity and enables efficient execution at both high and low levels of thread parallelism.
Proceedings ArticleDOI
Reducing peak power with a table-driven adaptive processor core
TL;DR: In this article, the authors proposed an adaptive processor architecture to reduce peak power by 25% with less than 5% performance loss, which can save 5.3% of total core area for decoupling capacitors.
Patent
On-chip sensor for measuring dynamic power supply noise of the semiconductor chip
Lew G. Chua-Eoan,Boris Andreev,Christopher Phan,Amirali Shayan,Xiaohua Kong,Mikhail Popovich,Mauricio Calle,Ik Joon Chang +7 more
TL;DR: In this article, an on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip and evaluates the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.
Proceedings ArticleDOI
3D stacked power distribution considering substrate coupling
Amirali Shayan,Xiang Hu,Wanping Zhang,Chung-Kuan Cheng,A. Ege Engin,Xiaoming Chen,Mikhail Popovich +6 more
TL;DR: A comprehensive modeling of the TSV and stacked power grid with frequency dependent parasitic is proposed and the analytical model considers the impact of the substrate coupling between the TSVs and layers grid.
Proceedings ArticleDOI
Reliability aware through silicon via planning for 3D stacked ICs
Amirali Shayan,Xiang Hu,He Peng,Chung-Kuan Cheng,Wenjian Yu,Mikhail Popovich,Thomas R. Toms,Xiaoming Chen +7 more
TL;DR: This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs) by modeled and extracted in frequency domain which includes the impact of skin effect.