Closed-loop stimulation of many neurological disorders, such as epilepsy, is an emerging technology and regarded as a promising alternative for surgical and drug treatment. In this paper, a real-time seizure detection algorithm based on STFT and support vector machine (SVM) and its field-programmable gate array (FPGA) implementation are proposed. With a two-stage patient-specific channel selection and feature selection mechanism, those redundant and uncorrelated spectral features are removed from the entire feature set. The evaluation results on CHB-MIT epilepsy database show that the mean detection latency of the proposed algorithm is 6 s, the sensitivity is 98.4%, and the false detection rate is 0.356/h. The performance of our proposed algorithm is comparable to other existing seizure detection algorithms. Moreover, we implement the proposed seizure detection algorithm on Xilinx Zynq-7000 XC7Z020 with high level synthesis. Each classification of the input electroencephalography signal can be finished within 313 $\mu \text{s}$ , and the power consumption of the programmable logic is only 380 mW at 100 MHz. In hardware implementation, an optimization strategy for the nested-loop structure within nonlinear SVM is proposed to improve pipeline efficiency. Compared with existing method, the experimental result shows that our method can speed up the nonlinear SVM by $1.70\times $ , $1.53\times $ , $1.37\times $ , and $1.26\times $ with the unroll factor equal to 1–4 at the same DSP utilization rate. The evaluation results affirm the possibility of integrating the proposed algorithm and FPGA implementation into a wearable seizure control device.

Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM

Fast Fourier Transform (FFT) is generally implemented on reconfigurable hardware in several signal processing or digital communication applications. It can be considered the most time and resource consuming operations due to the need of complex operations. The main of this manuscript is to investigate the contribution of High Level Synthesis (HLS) techniques on the implementation of real time FFT algorithms using field programmable gate arrays (FPGAs). In particular, this study focuses on communication systems incorporating filter-based-multicarrier modulations (FBMC), a promising candidate for the 5G technology. In order to evaluate the contribution of HLS, we implemented and tested various combinations such as: 8 and 16 points radix-2 and radix-4 FFT using finite precision, HLS tools and HDL while prompting parallelization, pipelining and hardware reuse architectures.

FFT Radix-2 and Radix-4 FPGA Acceleration Techniques Using HLS and HDL for Digital Communication Systems

Field-programmable gate array (FPGA)-based simulation system is applied in real-time electromagnetic transient (EMT) simulation for small time-step simulation. However, the FPGA-based simulation system requires handcrafted hardware description language (HDL) and significant design efforts. This paper explores FPGA-based EMT real-time simulation system design using high-level synthesis (HLS) technology to accelerate the design process and improve the flexibility, because high-level language can be transferred into HDL using HLS. Furthermore, loop unroll and pipeline optimisation directives are analysed and applied for HLS to improve the computation speed of the components. The system can simulate various components, including switches, R-L-C, voltage sources, current sources, and transmission lines. Especially, the system adopting double-precision floating-point calculation can support the network with 74 nodes and achieve 2 us for each small time step on Xilinx Virtex7-690 T FPGA. Comparison of simulation results from offline simulation tools with those from the proposed simulation system validates the correctness of the FPGA-based EMT simulation system using HLS technology.

Exploration of FPGA-based electromagnetic transient real-time simulation system design using high-level synthesis

High-Level Synthesis (HLS) tools are an attractive option for fast prototyping and implementation of hardware accelerators performing digital signal processing algorithms such as the Fast Fourier Transform (FFT). However, the efficiency and the performance level of the generated architectures depend on the behavioral models. Moreover, Design Space Exploration features enabled by HLS tools are limited by the behavioral model parallelization features. In this paper, a generic FFT behavioral model usable within HLS tools is presented. Its configurable parameters enable to cover a broader architectural space by taking advantage of more parallelization strategies contrary of related works. Thus, this designed model can produce low-complexity architectures up to high throughput ones as highlighted by experimental results. 

High-throughput FFT architectures using HLS tools

Fifth generation (5G) is a new generation mobile communication system developed for the growing demand for mobile communication. Channel coding is an indispensable part of most modern digital communication systems, for it can improve the transmission reliability and anti-interference. In order to meet the requirements of 5G communication, a dual threshold self-corrected minimum sum (DT-SCMS) algorithm for low-density parity-check (LDPC) decoders is proposed in this paper. Besides, an architecture of LDPC decoders is designed. By setting thresholds to judge the reliability of messages, the DT-SCMS algorithm erases unreliable messages, improving the decoding performance and efficiency. Simulation results show that the performance of DT-SCMS is better than that of SCMS. When the code rate is 1/3, the performance of DT-SCMS has been improved by 0.2 dB at the bit error rate of 10 − 4 compared with SCMS. In terms of the convergence, when the code rate is 2/3, the number of iterations of DT-SCMS can be reduced by up to 20.46% compared with SCMS, and the average proportion of reduction is 18.68%.

Dual Threshold Self-Corrected Minimum Sum Algorithm for 5G LDPC Decoders

High level synthesis tools are an attractive option for rapid prototyping and implementation of hardware designs. In this paper we present a case study of using such a tool for the design and implementation of an FFT core for use in a wireless modem. The optimizations used for directing the conversion of C code to hardware are discussed and the impact of the different directives is analyzed. The resulting hardware architecture is competitive with the highly optimized IP core available from Xilinx for their FPGAs in terms of the hardware requirements while achieving a slightly better latency for the same configuration.

Amit Salaskar

Papers

FFT/IFFT implementation using Vivado™ HLS